2,049 research outputs found

    A 39-GHz Doherty-Like Power Amplifier with 22-dBm Output Power and 21% Power-Added Efficiency at 6-dB Power Back-Off

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    © 2024, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/JETCAS.2024.3351075The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical loadmodulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non-50 Ω load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the SLMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power (Psat) with a maximum poweradded efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVMrms) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadratureamplitude- modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.Peer reviewe

    SerIOS: Enhancing Hardware Security in Integrated Optoelectronic Systems

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    Silicon photonics (SiPh) has different applications, from enabling fast and high-bandwidth communication for high-performance computing systems to realizing energy-efficient optical computation for AI hardware accelerators. However, integrating SiPh with electronic sub-systems can introduce new security vulnerabilities that cannot be adequately addressed using existing hardware security solutions for electronic systems. This paper introduces SerIOS, the first framework aimed at enhancing hardware security in optoelectronic systems by leveraging the unique properties of optical lithography. SerIOS employs cryptographic keys generated based on imperfections in the optical lithography process and an online detection mechanism to detect attacks. Simulation and synthesis results demonstrate SerIOS's effectiveness in detecting and preventing attacks, with a small area footprint of less than 15% and a 100% detection rate across various attack scenarios and optoelectronic architectures, including photonic AI accelerators

    Toward an active CMOS electronics-photonics platform based on subwavelength structured devices

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    The scaling trend of microelectronics over the past 50 years, quantified by Moore’s Law, has faced insurmountable bottlenecks, necessitating the use of optical communication with its high bandwidth and energy efficiency to further improve computing performance. Silicon photonics, compatible with CMOS platform manufacturing, presents a promising means to achieve on-chip optical links, employing highly sensitive microring resonator devices that demand electronic feedback and control due to fabrication variations. Achieving the full potential of both technologies requires tight integration to realize the ultimate benefits of both realms of technology, leading to the convergence of microelectronics and photonics. A promising approach for achieving this convergence is the monolithic integration of electronics and photonics on CMOS platforms. A critical milestone was reached in 2015 with the demonstration of the first microprocessor featuring photonic I/O (Chen et al, Nature 2015), accomplished by integrating transistors and photonic devices on a single chip using a monolithic CMOS silicon-on-insulator (SOI) platform (GlobalFoundries 45RFSOI, 45 nm SOI process) without process modifications, thus known as the "zero-change" approach. This dissertation focuses on leveraging the fabrication capabilities of advanced monolithic electronic-photonic 45 nm CMOS platforms, specifically high-resolution lithography and small feature size doping implants, to realize photonic devices with subwavelength features that could potentially provide the next leap in integrated optical links performance, beyond microring resonator based links. Photonic crystal (PhC) nanobeam cavities can support high-quality resonance modes while confining light in a small volume, enhancing light-matter interactions and potentially enabling ultimate efficiencies in active devices such as modulators and photodetectors. However, PhC cavities have been overshadowed by microring resonators due to two challenges. First, their fabrication demands high lithography resolution, which excludes most standard SOI photonic platforms as viable options for creating these devices. Secondly, the standing-wave nature of PhC nanobeam cavities complicates their integration into wavelength-division multiplexing (WDM) optical links, causing unwanted reflections when coupled evanescently to a bus waveguide. In this work, we present PhC nanobeam cavities with the smallest footprint, largest intrinsic quality factor, and smallest mode volume to be demonstrated to date in a monolithic CMOS platform. The devices were fabricated in a 45 nm monolithic electronics–photonics CMOS platform optimized for silicon photonics, GlobalFoundries 45CLO, exhibiting a quality factor in excess of 100,000 the highest among fully cladded PhC nanobeam cavities in any SOI platform. Furthermore to eliminate reflections, we demonstrate an approach using pairs of PhC nanobeam cavities with opposite spatial mode symmetries to mimic traveling-wave-like ring behavior, enabling efficient and seamless WDM link integration. This concept was extended to realize a reflectionless microring resonator unit with two microrings operating as standing-wave cavities. Using this scheme with standing-wave microring resonators could lead to an optimum geometry for microring modulators with interdigitated p-n junctions in terms of modulation efficiency in a manner that allows for straightforward WDM cascading. This work also presents the first demonstration of resonant-structure-based modulators in the GlobalFoundries 45CLO platform. We report the first-ever demonstration of a PhC modulator in a CMOS platform, featuring a novel design with sub-wavelength contacts on one side allowing it to benefit from the "reflection-less"' architecture. Additionally, we also report the first demonstration of microring modulators. The most efficient devices exhibited electro-optical bandwidths up to 30 GHz, and 25 Gbps non-return-to-zero (NRZ) on-off-keyed (OOK) modulation with 1 dB insertion loss and 3.1 dB extinction ratio. Finally, as the complexity of silicon photonic systems-on-a-chip (SoC) increases to enable new applications such as low-energy data links, quantum optics, and neuromorphic computing, the need for in-situ characterization of individual components becomes increasingly important. By combining Near-field scanning optical microscopy (NSOM) with a flip-chip post-processing technique, this dissertation demonstrates a method to non-invasively perform NSOM scans of a photonic device within a large-scale CMOS-photonic circuit, without interfering with the performance and packaging of the photonics and electronics, making it a valuable tool for future development of high performance photonic circuits and systems

    6G Wireless Communications in 7-24 GHz Band: Opportunities, Techniques, and Challenges

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    The sixth generation (6G) wireless communication nowadays is seeking a new spectrum to inherit the pros and discard the cons of sub-6 GHz, millimeter-wave (mmWave), and sub-terahertz (THz) bands. To this end, an upper mid-band, Frequency Range (FR) spanning from 7 GHz to 24 GHz, also known as FR3, has emerged as a focal point in 6G communications. Thus, as an inexorable prerequisite, a comprehensive investigation encompassing spectrum utilization and channel modeling is the first step to exploit potential applications and future prospects of using this FR in the 6G ecosystem. In this article, we provide FR3 deployment insights into emerging technologies including non-terrestrial network (NTN), massive multi-input multi-output (mMIMO), reconfigurable intelligent surface (RIS), and joint communications and sensing (JCAS). Furthermore, leveraging ray-tracing simulations, our investigation unveils the channel characteristics in FR3 are close to those in the sub-6 GHz band. The analysis of RIS-aided communication shows a higher spectral efficiency achieved in FR3 compared to other FRs when using the same RIS size. Finally, challenges and promising directions are discussed for FR3-based communication systems.Comment: 7 pages, 5 figures, 1 tabl

    Beam scanning by liquid-crystal biasing in a modified SIW structure

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    A fixed-frequency beam-scanning 1D antenna based on Liquid Crystals (LCs) is designed for application in 2D scanning with lateral alignment. The 2D array environment imposes full decoupling of adjacent 1D antennas, which often conflicts with the LC requirement of DC biasing: the proposed design accommodates both. The LC medium is placed inside a Substrate Integrated Waveguide (SIW) modified to work as a Groove Gap Waveguide, with radiating slots etched on the upper broad wall, that radiates as a Leaky-Wave Antenna (LWA). This allows effective application of the DC bias voltage needed for tuning the LCs. At the same time, the RF field remains laterally confined, enabling the possibility to lay several antennas in parallel and achieve 2D beam scanning. The design is validated by simulation employing the actual properties of a commercial LC medium

    Learning Energy-Efficient Hardware Configurations for Massive MIMO Beamforming

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    Hybrid beamforming (HBF) and antenna selection are promising techniques for improving the energy efficiency~(EE) of massive multiple-input multiple-output~(mMIMO) systems. However, the transmitter architecture may contain several parameters that need to be optimized, such as the power allocated to the antennas and the connections between the antennas and the radio frequency chains. Therefore, finding the optimal transmitter architecture requires solving a non-convex mixed integer problem in a large search space. In this paper, we consider the problem of maximizing the EE of fully digital precoder~(FDP) and hybrid beamforming~(HBF) transmitters. First, we propose an energy model for different beamforming structures. Then, based on the proposed energy model, we develop an unsupervised deep learning method to maximize the EE by designing the transmitter configuration for FDP and HBF. The proposed deep neural networks can provide different trade-offs between spectral efficiency and energy consumption while adapting to different numbers of active users. Finally, to ensure that the proposed method can be implemented in practice, we investigate the ability of the model to be trained exclusively using imperfect channel state information~(CSI), both for the input to the deep learning model and for the calculation of the loss function. Simulation results show that the proposed solutions can outperform conventional methods in terms of EE while being trained with imperfect CSI. Furthermore, we show that the proposed solutions are less complex and more robust to noise than conventional methods.Comment: This preprint comprises 15 pages and features 15 figures. Copyright may be transferred without notic

    Design of Reconfigurable Intelligent Surfaces for Wireless Communication: A Review

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    Existing literature reviews predominantly focus on the theoretical aspects of reconfigurable intelligent surfaces (RISs), such as algorithms and models, while neglecting a thorough examination of the associated hardware components. To bridge this gap, this research paper presents a comprehensive overview of the hardware structure of RISs. The paper provides a classification of RIS cell designs and prototype systems, offering insights into the diverse configurations and functionalities. Moreover, the study explores potential future directions for RIS development. Notably, a novel RIS prototype design is introduced, which integrates seamlessly with a communication system for performance evaluation through signal gain and image formation experiments. The results demonstrate the significant potential of RISs in enhancing communication quality within signal blind zones and facilitating effective radio wave imaging

    Phased Array Antenna System Enabled by Liquid Metal Phase Shifters

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    A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator

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    A single-phase binary/quadrature phase-shift keying (BPSK/QPSK) demodulator basing on a phase-locked loop (PLL) is described. The demodulator relies on a linear characteristic a rising-edge RESET/SET flip-flop (RSFF) employed as a phase detector. The phase controller takes the average output from the RSFF and performs a sub-ranging/re-scaling operation to provide an input signal to a voltage-controlled oscillator (VCO). The demodulator is truly modular which theoretically can be extended for a multiple-PSK (m-PSK) signal. Symbol-error rate analysis has also been extensively carried out. The proposed BPSK and QPSK demodulators have been fabricated in a 0.18-mm digital complementary metal–oxide–semiconductor (CMOS) process where they operate from a single supply of 1.8 V. At a carrier frequency of 60 MHz, the BPSK and QPSK demodulators achieved maximum symbol rates of 25 and 12.5 Msymb/s while consuming 0.68 and 0.79 mW, respectively. At these maximum symbol rates, the BPSK and QPSK demodulators deliver symbol-error rates less than 7.9×10-10 and 9.8×10-10, respectively where their corresponding energy per bit figures were at 27.2 and 31.7 pJ
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