ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER

This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources. RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands. Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system. A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured. A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network

High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers

Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally serves as the primary part of the system, which heavily influences the system performance. This research concentrates on the designs of several important blocks of the receiver; multi-stage amplifier and low noise amplifier. Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and reduce the silicon area for the application where a large capacitive load exists. They were designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband application and the other for UWB application. A noise reduction technique is proposed for the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better linearity, lower power consumption, and reasonable noise performance. Finally a novel practical current injection built-in-test (BIT) technique is proposed for the RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error

High Performance RF and Basdband Analog-to-Digital Interface for Multi-standard/Wideband Applications

The prevalence of wireless standards and the introduction of dynamic standards/applications, such as software-defined radio, necessitate the next generation wireless devices that integrate multiple standards in a single chip-set to support a variety of services. To reduce the cost and area of such multi-standard handheld devices, reconfigurability is desirable, and the hardware should be shared/reused as much as possible. This research proposes several novel circuit topologies that can meet various specifications with minimum cost, which are suited for multi-standard applications. This doctoral study has two separate contributions: 1. The low noise amplifier (LNA) for the RF front-end; and 2. The analog-to-digital converter (ADC). The first part of this dissertation focuses on LNA noise reduction and linearization techniques where two novel LNAs are designed, taped out, and measured. The first LNA, implemented in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35Cm CMOS (Complementary metal-oxide-semiconductor) process, strategically combined an inductor connected at the gate of the cascode transistor and the capacitive cross-coupling to reduce the noise and nonlinearity contributions of the cascode transistors. The proposed technique reduces LNA NF by 0.35 dB at 2.2 GHz and increases its IIP3 and voltage gain by 2.35 dBm and 2dB respectively, without a compromise on power consumption. The second LNA, implemented in UMC (United Microelectronics Corporation) 0.13Cm CMOS process, features a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, which obtains a robust linearity improvement over process and temperature variations. The proposed linearization method is experimentally demonstrated to improve the IIP3 by 3.5 to 9 dB over a 2.5–10 GHz frequency range. A comparison of measurement results with the prior published state-of-art Ultra-Wideband (UWB) LNAs shows that the proposed linearized UWB LNA achieves excellent linearity with much less power than previously published works. The second part of this dissertation developed a reconfigurable ADC for multistandard receiver and video processors. Typical ADCs are power optimized for only one operating speed, while a reconfigurable ADC can scale its power at different speeds, enabling minimal power consumption over a broad range of sampling rates. A novel ADC architecture is proposed for programming the sampling rate with constant biasing current and single clock. The ADC was designed and fabricated using UMC 90nm CMOS process and featured good power scalability and simplified system design. The programmable speed range covers all the video formats and most of the wireless communication standards, while achieving comparable Figure-of-Merit with customized ADCs at each performance node. Since bias current is kept constant, the reconfigurable ADC is more robust and reliable than the previous published works

Analog FIR Filter Used for Range-Optimal Pulsed Radar Applications

Matched filter is one of the most critical block in radar applications. With different measured range and relative velocity of a target we will need different bandwidth of the matched filter to maximize the radar signal to noise ratio (SNR). Conventional matched filter designs incorporate surface acoustic wave (SAW) filters. However, it is not inherently tunable and will need multiple SAW filters with to change the bandwidth resulting in costly solutions. In this work, a novel method of implementing the matched filter with an analog FIR filter is proposed. The FIR filter provides a linear phase response which is suitable for radar applications. Analog FIR filters can be implemented in the discrete domain, requiring operational amplifiers, switches and capacitors. In this work, the FIR filter is implemented using a highly programmable operational transconductance amplifier with tunable transconductance gain. The operational amplifiers designed for the filter uses a fully differential source degeneration topology to increase the linearity; also capacitive degeneration was placed to compensate its high frequency response. An active continuous-time common mode feedback (CMFB) circuit is also presented. This circuit presents a much smaller load capacitance to the output of the amplifier, yielding a higher frequency response. To satisfy system specifications a 128-tap FIR system is implemented, which require over 128 amplifiers, 136 unity capacitors of 1pF each and 4760 switches. The functionality of the proposed architecture has been verified through schematic and behavior model simulations. In the simulation, the robustness of the FIR filter to process and temperature variation is also verified. The circuits were designed in the TowerJazz 180nm CMOS technology and fabricated on November 2013

Energy-efficient wireless sensors : fewer bits, Moore MEMS

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis. Page 184 blank.Includes bibliographical references (p. 171-183).Adoption of wireless sensor network (WSN) technology could enable improved efficiency across a variety of industries that include building management, agriculture, transportation, and health care. Most of the technical challenges of WSNs can be linked to the stringent energy constraints of each sensor node, where wireless communication and leakage energy are the doninant components of active and idle energy costs. To address these two limitations, this thesis adopts compressed sensing (CS) theory as a generic source coding framework to minimize the transmitted data and proposes the use of micro-electro-mechanical (MEM) relay technology to eliminate the idle leakage. To assess the practicality of adopting CS as a source coding framework we examine the inpact of finite resources, input noise, and wireless channel impairments on the compression and reconstruction performance of CS. We show that CS, despite being a lossy compression algorithm, can realize compression factors greater than loX with no loss in fidelity for sparse signals quantized to medium resolutions. We also model the hardware costs for implementing the CS encoder and results from a test chip designed in a 90 nm CMOS process that consumes only 1.9 [mu]W for operating frequencies below 20 kHz, verifies the models. The encoder is desioned to enable continuous, on-the-fly compression that is demonstrated on electroencephalography (EEG) and electrocardiogram (EKG) signals to show the applicability of CS. To address sub-threshold leakage, which limits the energy performance in CMOS-based sensor nodes, we develop design methodologies towards leveraging the zero leakage characteristics of MEM relays while overcoming their slower switching speeds. Projections on scaled relay circuits show the potential for greater than loX improvements in energy efficieicy over CMOS at up to 10-100 Mops for a variety of circuit sub-systems. Experimental results demonstrating functionality for several circuit building blocks validate the viability of the technology, while feedback from these results is used to refine the device design. Incorporating all of the design elements, w present simnulation results for our most recent test chip design which implements relay-based versions of the CS encoder circuits in a 0.25 jim lithographic process showing 5X improvement over our 90 nm CMOS design.by Fred Chen.Ph.D

RF Frontend for Spectrum Analysis in Cognitive Radio

Advances in wireless technology have sparked a plethora of mobile communication standards to support a variety of applications. FCC predicts a looming crisis due to the exponentially growing demand for spectrum and it recommends to increase the efficiency of spectrum utilization. Cognitive Radio (CR) is envisioned as a radio technology which detects and exploits empty spectrum to improve the quality of communication. Spectrum analyzer for detecting spectrum holes is a key component required for implementing cognitive radio. Mitola's vision of using an RF Analog-to-Digital (ADC) to digitize the entire spectrum is not yet a reality. The traditional spectrum analysis technique based on a RF Front end using an LO Sweep is too slow, making it unsuitable to track fast hopping signals. In this work, we demonstrate an RF Frontend that can simplify the ADC's requirement by splitting the input spectrum into multiple channels. It avoids the problem of PLL settling by incorporating LO synthesis within the signal path using a concept called Iterative Down Converter. An example 0.75GHz-11.25GHz RF Channelizer is designed in 65nm Standard CMOS Process. The channelizer splits the input spectrum (10.5GHz bandwidth) into seven channels (each of bandwidth 1.5GHz). The channelizer shows the ability to rapidly switch from one channel to another (within a few ns) as well as down-converting multiple channels simultaneously (concurrency). The channelizer achieves a dynamic range of 54dB for a bandwidth of 10.5GHz, while consuming 540mW of power. Harmonic rejection mixer plays a key role in a broadband receiver. A novel order scalable harmonic rejection mixer architecture is described in this research. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. While cognitive radio solves the spectrum efficiency problem in frequency domain, the electronic beam steering provides a spatial domain solution. Electronic beam forming using phased arrays have been claimed to improve spectrum efficiency by serving more number of users for a given bandwidth. A LO path phase-shifter with frequency-doubling is demonstrated for WiMAX applications

RF Frontend for Spectrum Analysis in Cognitive Radio

Advances in wireless technology have sparked a plethora of mobile communication standards to support a variety of applications. FCC predicts a looming crisis due to the exponentially growing demand for spectrum and it recommends to increase the efficiency of spectrum utilization. Cognitive Radio (CR) is envisioned as a radio technology which detects and exploits empty spectrum to improve the quality of communication. Spectrum analyzer for detecting spectrum holes is a key component required for implementing cognitive radio. Mitola's vision of using an RF Analog-to-Digital (ADC) to digitize the entire spectrum is not yet a reality. The traditional spectrum analysis technique based on a RF Front end using an LO Sweep is too slow, making it unsuitable to track fast hopping signals. In this work, we demonstrate an RF Frontend that can simplify the ADC's requirement by splitting the input spectrum into multiple channels. It avoids the problem of PLL settling by incorporating LO synthesis within the signal path using a concept called Iterative Down Converter. An example 0.75GHz-11.25GHz RF Channelizer is designed in 65nm Standard CMOS Process. The channelizer splits the input spectrum (10.5GHz bandwidth) into seven channels (each of bandwidth 1.5GHz). The channelizer shows the ability to rapidly switch from one channel to another (within a few ns) as well as down-converting multiple channels simultaneously (concurrency). The channelizer achieves a dynamic range of 54dB for a bandwidth of 10.5GHz, while consuming 540mW of power. Harmonic rejection mixer plays a key role in a broadband receiver. A novel order scalable harmonic rejection mixer architecture is described in this research. A proof-of-principle prototype has been designed and fabricated in a 45nm SOI technology. Experimental results demonstrate an operation range of 0.5GHz to 1.5GHz for the LO frequency while offering harmonic rejection better than 55dB for the 3rd harmonic and 58dB for the 5th harmonic across LO frequencies. While cognitive radio solves the spectrum efficiency problem in frequency domain, the electronic beam steering provides a spatial domain solution. Electronic beam forming using phased arrays have been claimed to improve spectrum efficiency by serving more number of users for a given bandwidth. A LO path phase-shifter with frequency-doubling is demonstrated for WiMAX applications

Contribution à la conception d'un récepteur mobile failble coût et faible consommation dans la bande Ku pour le standard DVB-S

Cette thèse présente une étude de faisabilité d'un récepteur faible coût et faible consommation pour l'extension du standard DVS-S à la mobilité. L'objectif de ce projet est de proposer de solutions pour lever les verrous technologiques quant à la réalisation d'un tel système en technologie CMOS 65 nm. Ce manuscrit de thèse articulé autour de quatre chapitres décrit toutes les étapes depuis la définition des spécifications du réseau d'antennes et de la chaîne de réception jusqu'à la présentation de leurs performances, en passant par l'étude de leurs architectures et de la conception des différents blocs. Suite à l'étude au niveau système et au bilan de liaison, le démonstrateur envisagé est constitué d'un réseau d'antennes (huit sous-réseaux de huit antennes microruban) suivi de la mise en parallèle de huit chemins unitaires pour satisfaire les exigences (Gain, facteur de bruit, rapport signal-à-bruit...) de l'application visée. Ce travail a abouti à la démonstration de la faisabilité d'une architecture innovante. Par ailleurs, nous avons aussi démontré sa non-application pour le standard DVB-S en raison des limitations en bruit de la technologie CMOS. Cependant des pistes existent pour améliorer le rapport signal-à-bruit du démonstrateur, à savoir l'utilisation d'un LNA (Low Noise Amplifier) avec une technologie compétitive en bruit et/ou d'un traitement du signal après la démodulation en bande par un processeur analogique.This work focuses on the faisability of a low cost and low power receiver in order to extend the DVB-S standard to mobility. The objective of this project is to suggest solutions to overcome technological bottlenecks fot the realization of such a demonstrator with 65 nm CMOS technology. This report composed of four chapters, describes all steps from the specification definition to the performances of the antenna array and the receiver through the architecture study and the different blocks design. [...]BORDEAUX1-Bib.electronique (335229901) / SudocSudocFranceF