3 research outputs found
Schedule-Aware Performance Estimation of Communication Architecture for Efficient Design Space Exploration
In this paper,we are concerned about performance estimation
of bus-based communication architectures assuming that
task partitioning and scheduling on processing elements are already
determined. Since communication overhead is dynamic and
unpredictable due to bus contention, a simulation-based approach
seems inevitable for accurate performance estimation. However,
it is too time-consuming to be used for exploring the wide design
space of bus architectures. We propose a static performance-estimation
technique based on a queueing analysis assuming that the
memory traces and the task schedule information are given. We
use this static estimation technique as the first step in our design
space exploration framework to prune the design space drastically
before applying a simulation-based approach to the reduced design
space. Experimental results show that the proposed technique
is several orders of magnitude faster than a trace-driven simulation
while keeping the estimation error within 10% consistently in
various communication architecture configurations.This work was supported by the National Research Laboratory under Program
M1-0104-00-0015, Brain Korea 21 Project, and the IT-SoC project. ICT
at Seoul National University provided research facilities for this study