Analysis and study of powerefficient sar adc for active rfid sensor

This thesis introduced an energy-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) specialized to the active sensors for low-power radio frequency identification (RFID) tag system. As part of the Internet of Things (IoT) transformation, RFID is widely used. In the application where the power supply is limited, power consumption is always a notable criterion as analog circuits such as the ADC circuit, regulator circuit, rectifier circuit and radio frequency (RF) are the common power demanding parts in the system. Normally, the requirement for a longer battery performance is closely related to low-power consumption. For the application active RFID sensor in which requires low to moderate resolution and speed as well as low-power consumption, SAR is usually used as its part of the ADC circuit. Therefore, the power-efficient SAR ADC is presented in this work. The block of SAR ADCs such as the comparator block, digital-to-analog converter (DAC) block, and sampler block is designed to meet the requirement of a low-power consumption performance measurement. This thesis at first will explores the differences between multiple ADC techniques in the previous works. The proposed SAR ADC is presented to enhance the power consumption of SAR ADC in the active RFID sensor application through the implementation of a single-input comparator with the switched-capacitor DAC. In this form of architecture, there is only one input to the comparator, and only one set and a split sampling capacitor in the switched capacitor DAC to generate the required reference levels. The difference in input and output voltage of the proposed SAR ADC is the indication for the low-power design. The influence of parasitic capacitance is reduced to the extent of becoming a non-factor. The parameters of the SAR ADC are the resolution of 8-bit, the sampling frequency of 500 kHz, the supply voltage of 1 V, and the 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology. The power consumption of the proposed SAR ADC is 2.3 μW which is estimated at around 25.8% improvement from the previous work. The demands for low-power consumption of RFID active sensor is well examined. The validity of the proposed design has been proven by the simulation results

Radio frequency energy harvesting for autonomous systems

A thesis submitted to the University of Bedfordshire in partial fulfilment of the requirements for the degree of Doctor of PhilosophyRadio Frequency Energy Harvesting (RFEH) is a technology which enables wireless power delivery to multiple devices from a single energy source. The main components of this technology are the antenna and the rectifying circuitry that converts the RF signal into DC power. The devices which are using Radio Frequency (RF) power may be integrated into Wireless Sensor Networks (WSN), Radio Frequency Identification (RFID), biomedical implants, Internet of Things (IoT), Unmanned Aerial Vehicles (UAVs), smart meters, telemetry systems and may even be used to charge mobile phones. Aside from autonomous systems such as WSNs and RFID, the multi-billion portable electronics market – from GSM phones to MP3 players – would be an attractive application for RF energy harvesting if the power requirements are met. To investigate the potential for ambient RFEH, several RF site surveys were conducted around London. Using the results from these surveys, various harvesters were designed and tested for different frequency bands from the RF sources with the highest power density within the Medium Wave (MW), ultra- and super-high (UHF and SHF) frequency spectrum. Prototypes were fabricated and tested for each of the bands and proved that a large urban area around Brookmans park radio centre is suitable location for harvesting ambient RF energy. Although the RFEH offers very good efficiency performance, if a single antenna is considered, the maximum power delivered is generally not enough to power all the elements of an autonomous system. In this thesis we present techniques for optimising the power efficiency of the RFEH device under demanding conditions such as ultra-low power densities, arbitrary polarisation and diverse load impedances. Subsequently, an energy harvesting ferrite rod rectenna is designed to power up a wireless sensor and its transmitter, generating dedicated Medium Wave (MW) signals in an indoor environment. Harvested power management, application scenarios and practical results are also presented

Fractional-N Synthesizer Architectures with Digital Phase Detection.

During the last decade there has been unprecedented growth in the use of portable wireless communications devices for applications as diverse as medical implants, industrial inventory control, and consumer electronics. If these communication devices are to be low power, flexible, and reconfigurable, new radio architectures are needed which take advantage of the major strength of state-of-the-art digital manufacturing processes; that is the ability to build large, complex low power signal processing circuits, with extremely fast clocking speeds. However, traditional radio architectures rely on analog techniques which are ill suited for the use in modern highly integrated digital systems. A critical component of a radio system is the frequency synthesizer, a circuit which can accurately synthesize and modulate high frequency signals. Traditional synthesizers still utilize a significant amount of analog circuitry. In this work, techniques are developed to replace this analog circuitry with digital equivalents. To do this, a digital phase detection scheme for a Fractional-N Phase Lock Loop (FPLL) is presented. The all-digital phase detector can be used as an alternative to a conventional analog-intensive phase detector, charge pump and loop filter blocks. Another limitation of traditional synthesizers is the difficulty in modulating the frequency of the output signal at speeds larger the FPLL’s bandwidth. A new technique is developed for modulating the output frequency of the FPLL at rates significantly faster than the loop bandwidth would typically allow. A digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated. The new scheme does not compromise on the frequency accuracy of the output signal. The key ideas presented have been proven in a proof of concept design. A prototype 2.2GHz fractional-N synthesizer, incorporating the digital phase detector and sampling scheme is presented as a proof of concept. Although the loop bandwidth is only 142kHz, an FSK modulation rate of 927.5kbs is achieved. The prototype is implemented in 0.13μm CMOS and consumes 14mW from a 1.4V supply.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60888/1/mferriss_1.pd

A new transponder architecture for long range telemetry applications.

This report presents a new architecture that can achieve long range wireless power and high data rate data telemetry. The architecture described in the report achieves long range operation with a fully CMOS compatible integrated circuit, unlike current state-of-the-art methods, and can be used in various applications such as long range passive RFID device, wirelessly power sensors and sensor networks. An RF-to-DC converter rectifies the incident RF signal and stores it on a storage capacitor. The voltage stored on the capacitor is used as the supply for the rest of the system blocks. The RF-to-DC converter generates DC output voltages much higher than the incident RF signal amplitude. The converter needs -12.3 dBm of incident RF power to generate a 3VDC supply voltage. This corresponds to an operational range of more than 18.3 meters. A low power mode selector circuit constantly monitors the voltage stored on the storage capacitor and generates an enable signal when there is enough voltage stored to operate the system blocks. The system is enabled when the voltage on the capacitor exceeds a high threshold and is disabled when it drops below a lower threshold. A new system clock generation scheme is proposed in this architecture. A fully integrated LC oscillator injection locked to the incident RF signal is used to extract a system clock in synchronization with the base station. The LC oscillator generates high purity system clock with low power consumption. Three prototypes have been designed based on this architecture. All devices are fabricated in TSMC 0.25mum mixed-mode process. The first one is a long range RFID device that transmits an 8-bit ID on an AM modulated 900 MHz carrier at 56 Mbits/sec. The second one is a wireless temperature sensor, which transmits the ambient temperature information as a shift of the 2.3 GHz carrier. The sensor has 126ppm/°C sensitivity with 0.983 linearity. The third prototype is a long range telemetry device with an integrated ADC. It transmits a combination of the output of a 5-bit ADC and a 3-bit ID word on a BPSK modulated 900 MHz carrier at 8Mbits/sec.Ph.D.Applied SciencesElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/125124/2/3186670.pd