3 research outputs found
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μ λ ₯μ 5.6 % λ° λ©΄μ μΌλ‘ 5.3 % μ€μΌ μ μμμ λ³΄μ¬ μ£Όμλ€.In this paper, we introduce dynamic power optimization techniques applicable for
various design stage from standard cell to placement stage. This work firstly investiοΏ½gates the problem of how designing data-driven (i.e., toggling based) clock gating can
be closely integrated with the synthesis of flip-flops, which has never been addressed
in the prior clock gating works. Our key observation is that some internal part of a
flip-flop cell can be reused to generate its clock gating enable signal. Based on this,
we propose a newly optimized flip-flop wiring structure, called eXOR-FF, in which
an internal logic can be reused for every clock cycle to decide if the flip-flop is to
be activated or inactivated through clock gating, thereby achieving area saving (thus,
leakage as well as dynamic power saving) on every pair of flip-flop and its toggling
detection logic. Then, we propose a comprehensive methodology of placement/timingοΏ½aware clock gating exploration that provides two unique strengths: best suited for maxοΏ½imally exploiting the benefit of eXOR-FFs and precise analyses on the decomposition
of power consumptions and timing impact, and translating them into cost functions in
core engine of clock gating exploration.
Through experiments with benchmark circuits in ISCAS89, ITC89, ITC99 and
IWLS 2005, it is shown that our proposed method is able to reduce the total power by
5.6% and total cell area by 5.3% compared with the previous data-driven clock gating
method in [1].Abstract
Contents
List of Tables
List of Figures
1 Introduction
1.1 Power Consumption in CMOS Digital Design
1.2 Low Power Design Methodologies
1.3 Contribution of This Thesis
2 Preliminary and Motivations 6
2.1 Background
2.2 Observation on Area and Power Saving
2.3 Observation on Timing Impact
3 Redesign of Flip-flops Specialized for Clock Gating
3.1 Observation on Area Impact
4 Placement-aware Clock Gating Methodology Utilizing eXOR-FF Cells
4.1 Overall Design Flow
4.2 Cost Formulation for Conventional Clock Gating
4.3 Cost Formulation for Our Clock Gating using eXOR-FFs
5 Experiments
5.1 Experimental Setup
5.2 Experimental Results
5.3 Comparing with Industry Algorithm
6 Conclusion
Abstract (In Korean)Maste
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μ§μ° μκ°μ΄λ©°, λ λ²μ§Έλ‘ λ©ν°νλ μ λλ¨Ήμ 루νκ° μλ μν 보쑴 ν립-νλμ μ΅μ ν λΆκ°λ₯μ±μ΄λ€. κΈ°μ‘΄ λ°©λ²λ€μμλ μν 보쑴μ μν μ μ₯ 곡κ°μ μ΅μννκΈ° μν΄ κΈ΄ μ¨μ΄ν¬μ
μ§μ° μκ°μ΄ νμμ μ΄μλ€. κ·Έλ¦¬κ³ λλ¨Ήμ 루νκ° μλ ν립-νλμ μ΅μ νν μ μλ λμμΌλ‘ λ€λ£¨μ΄μ‘λ€. κ·Έλ¬λ μΌλ°μ μΌλ‘ νλμ¨μ΄ κΈ°μ μΈμ΄(HDL)λ‘λΆν° μμ±λλ λλ¨Ήμ 루νλ₯Ό μ§λ ν립-νλμ 무μν μ μμ μ λλ‘ μ μ μμ΄ μλλ€. 첫 λ²μ§Έ νκ³λ₯Ό ν΄κ²°νκΈ° μν λ°©λ²μΌλ‘ λ³Έ λ
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μ§μ° μκ°μ λ ν΄λ μ¬μ΄ν΄λ‘ μ ννλ©΄μλ μν 보쑴μ μν μ μ₯ 곡κ°μ ν¨μ¨μ μΌλ‘ μ μ½ν μ μμμ 보μΈλ€. κ·Έλ¦¬κ³ λ λ²μ§Έ νκ³λ₯Ό 극볡νκΈ° μν΄μ λλ¨Ήμ 루νλ₯Ό μ§λ ν립-νλμ΄ ν¬ν¨λ λ ν립-νλ μμ μνλ₯Ό 볡μν μ μλ 2λ¨ μν 보쑴 μ μ΄ λ°©μμ μ μνλ€. λν μ£Όμ΄μ§ νλ‘μμ μΆ©λμμ΄ λμμ μ‘΄μ¬ν μ μλ ν립-νλ μμ μ΅λλ‘ μΆμΆνκΈ° μν΄ λ
립 μ§ν© λ¬Έμ (independent set problem)κΈ°λ°μ μ°μ°λ²λ μ μνλ€. λ²€μΉλ§ν¬ νλ‘μ λν μ€ν κ²°κ³Όλ λ³Έ λ
Όλ¬Έμμ μ μλ λ°©λ²μ΄ μ¨μ΄ν¬μ
μ§μ° μκ°μ λ ν΄λ μ¬μ΄ν΄λ‘ μ ννλ©΄μλ μν 보쑴μ νμν μ μ₯ 곡κ°κ³Ό νμλ₯Ό κ°μμν€λλ° λ§€μ° ν¨κ³Όμ μμ 보μ¬μ€λ€.Low power design is of great importance in modern system-on-chips (SoCs). This dissertation studies on low power design methodologies for saving dynamic and static power consumption. Precisely, we unveil two novel techniques of cost effective low power design.
Firstly, we propose a novel clock gating method for reducing the dynamic power consumption. Flip-flop's input data toggling based clock gating is one of the most commonly used clock gating methods, in which one critical and inherent limitation is the sharp increase of gating logic as more flip-flops are involved in gating. In this dissertation, we propose a new clock gating method to overcome this limitation. Specifically, (1) we analyze the resources of gating logic in the input data toggling based clock gating, from which an ineffectiveness in resource utilization is observed and we propose a new clock gating technique called flip-flop state driven clock gating which completely eliminates the essential and expensive component of XOR gates for detecting input toggling of flip-flops; (2) we provide the supporting logic circuitry of our proposed XOR-free clock gating, confirming its safe applicability through a comprehensive timing analysis; (3) we propose, based on the flip-flops' state profile, a clock gating methodology that seamlessly combines our flip-flop state based clock gating with the toggling based clock gating. Through experiments with benchmark circuits, it is confirmed that our clock gating method is very effective in reducing power, which otherwise the toggling based clock gating shall miss the power saving opportunity, while meeting all timing constraints.
Secondly, for reducing the static power consumption, we solve two critical limitations of the conventional approaches to the allocation of state retention storage for power gated circuits. Those are (1) the long wakeup delay caused by the senseless use of multi-bit retention flip-flops (MBRFFs) and (2) the inability to optimize retention flip-flops for the flip-flops with mux-feedback loop. It should be noted that the conventional approaches have regarded the long wakeup delay as an inevitable consequence of maximizing the reduction of total storage size for state retention while they have treated the flip-flops with mux-feedback loop (called self-loop flip-flop) as nonoptimizable component, but practically, the self-loop flip-flops synthesized from hardware description language (HDL) code are not far from a small amount and thus, can in no way be negligible. More precisely, for solving (1), we show that the use of MBRFFs with up to two bits, consequently, constraining the wakeup delay to no more than two clock cycles, is enough to maintain the high reduction of total retention storage and for solving (2), we devise a 2-phase retention control mechanism for a pair of flip-flops, one of which has self-loop, by which just a single retention bit can be used to restore state of the two flip-flops, and propose an independent set based algorithm for maximally extracting the non-conflict pairs from circuits. Through experiments with benchmark circuits, it is shown that our proposed method is very effective against reducing the state retention storage and the power consumption compared with the existing best MBRFF allocation while the wakeup delay is strictly limited to two clock cycles.1 INTRODUCTION 1
1.1 Clock Gating 1
1.2 Power Gating and State Retention 3
1.3 Multi-bit Retention Registers 4
1.4 Contributions of This Dissertation 6
2 FLIP-FLOP STATE DRIVEN CLOCK GATING: CONCEPT, DESIGN, AND METHODOLOGY 9
2.1 Motivations 9
2.1.1 Toggling based Clock Gating 9
2.1.2 Area and Power by Clock Gating 10
2.2 The Proposed Clock Gating 13
2.2.1 Concept of Flip-flop State Driven Clock Gating 13
2.2.2 Design of Gating Logic Circuitry 17
2.2.3 Integrated Clock Gating Methodology 22
2.2.4 Cost Formulation 23
2.3 Experiments 25
2.3.1 Experimental Setup 25
2.3.2 Experimental Results 26
3 ALGORITHM AND DESIGN OPTIMIZATION OF ALLOCATING MULTI-BIT RETENTION FLIP-FLOPS FOR POWER GATED CIRCUITS 32
3.1 Motivations 32
3.1.1 Flip-flops with Mux-feedback Loop 32
3.1.2 Impact of Wakeup Delay 37
3.2 The Proposed Allocation Algorithm 39
3.3 Design of Multi-Bit Retention Flip-Flop and Multi-Bit Extension 48
3.3.1 Multi-Bit Retention Flip-Flop 48
3.3.2 Multi-Bit Flip-Flop Extension 52
3.4 Experiments 54
3.4.1 Experimental Setup 54
3.4.2 Experimental Results 57
4 CONCLUSIONS 65
4.1 Flip-flop State Driven Clock Gating: Concept, Design, and Methodology 65
4.2 Algorithm and Design Optimization of Allocating Multi-bit Retention Flip-flops for Power Gated Circuits 66
Abstract (In Korean) 71Docto