8x8 Reconfigurable quantum photonic processor based on silicon nitride waveguides

The development of large-scale optical quantum information processing circuits ground on the stability and reconfigurability enabled by integrated photonics. We demonstrate a reconfigurable 8x8 integrated linear optical network based on silicon nitride waveguides for quantum information processing. Our processor implements a novel optical architecture enabling any arbitrary linear transformation and constitutes the largest programmable circuit reported so far on this platform. We validate a variety of photonic quantum information processing primitives, in the form of Hong-Ou-Mandel interference, bosonic coalescence/anticoalescence and high-dimensional single-photon quantum gates. We achieve fidelities that clearly demonstrate the promising future for large-scale photonic quantum information processing using low-loss silicon nitride.Comment: Added supplementary materials, extended introduction, new figures, results unchange

A Lightweight McEliece Cryptosystem Co-processor Design

Due to the rapid advances in the development of quantum computers and their susceptibility to errors, there is a renewed interest in error correction algorithms. In particular, error correcting code-based cryptosystems have reemerged as a highly desirable coding technique. This is due to the fact that most classical asymmetric cryptosystems will fail in the quantum computing era. Quantum computers can solve many of the integer factorization and discrete logarithm problems efficiently. However, code-based cryptosystems are still secure against quantum computers, since the decoding of linear codes remains as NP-hard even on these computing systems. One such cryptosystem is the McEliece code-based cryptosystem. The original McEliece code-based cryptosystem uses binary Goppa code, which is known for its good code rate and error correction capability. However, its key generation and decoding procedures have a high computation complexity. In this work we propose a design and hardware implementation of an public-key encryption and decryption co-processor based on a new variant of McEliece system. This co-processor takes the advantage of the non-binary Orthogonal Latin Square Codes to achieve much smaller computation complexity, hardware cost, and the key size.Comment: 2019 Boston Area Architecture Workshop (BARC'19

Superconducting Quantum Computing: A Review

Over the last two decades, tremendous advances have been made for constructing large-scale quantum computers. In particular, the quantum processor architecture based on superconducting qubits has become the leading candidate for scalable quantum computing platform, and the milestone of demonstrating quantum supremacy was first achieved using 53 superconducting qubits in 2019. In this work, we provide a brief review on the experimental efforts towards building a large-scale superconducting quantum computer, including qubit design, quantum control, readout techniques, and the implementations of error correction and quantum algorithms. Besides the state of the art, we finally discuss future perspectives, and which we hope will motivate further research.Comment: Updated version, Typos corrected, New references added, New discussions adde

On the Quantum Performance Evaluation of Two Distributed Quantum Architectures

Distributed quantum applications impose requirements on the quality of the quantum states that they consume. When analyzing architecture implementations of quantum hardware, characterizing this quality forms an important factor in understanding their performance. Fundamental characteristics of quantum hardware lead to inherent tradeoffs between the quality of states and traditional performance metrics such as throughput. Furthermore, any real-world implementation of quantum hardware exhibits time-dependent noise that degrades the quality of quantum states over time. Here, we study the performance of two possible architectures for interfacing a quantum processor with a quantum network. The first corresponds to the current experimental state of the art in which the same device functions both as a processor and a network device. The second corresponds to a future architecture that separates these two functions over two distinct devices. We model these architectures as Markov chains and compare their quality of executing quantum operations and producing entangled quantum states as functions of their memory lifetimes, as well as the time that it takes to perform various operations within each architecture. As an illustrative example, we apply our analysis to architectures based on Nitrogen-Vacancy centers in diamond, where we find that for present-day device parameters one architecture is more suited to computation-heavy applications, and the other for network-heavy ones. Besides the detailed study of these architectures, a novel contribution of our work are several formulas that connect an understanding of waiting time distributions to the decay of quantum quality over time for the most common noise models employed in quantum technologies. This provides a valuable new tool for performance evaluation experts, and its applications extend beyond the two architectures studied in this work

Constructing 2D and 3D cluster states with photonic modules

Large scale quantum information processing (QIP) and distributed quantum computation require the ability to perform entangling operations on a large number of qubits. We describe a new photonic module which prepares, deterministically, photonic cluster states using an atom in a cavity as an ancilla. Based on this module we design a network for constructing 2D cluster states and then we extend the architecture to 3D topological cluster states. Advantages of our design include a passive switching mechanism and the possibility of using global control pulses for the atoms in the cavity. The architecture described here is well suited for integrated photonic circuits on a chip and could be used as a basis of a future quantum optical processor or in a quantum repeater node