STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS

Microelectronic devices and systems have been extensively utilized in a variety of radiation environments, ranging from the low-earth orbit to the ground level. A high-energy particle from such an environment may cause voltage/current transients, thereby inducing Single Event Effect (SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975, this community has made tremendous progress in investigating the mechanisms of SEE and exploring radiation tolerant techniques. However, as the IC technology advances, the existing hardening techniques have been rendered less effective because of the reduced spacing and charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has identified radiation-induced soft errors as the major threat to the reliable operation of electronic systems in the future. In digital systems, hardening techniques of their core components, such as latches, logic, and clock network, need to be addressed. Two single event tolerant latch designs taking advantage of feedback transistors are presented and evaluated in both single event resilience and overhead. These feedback transistors are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in a larger feedback delay and higher single event tolerance. On the other hand, these extra transistors are turned ON when the cell is in the write mode. As a result, no significant write delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section when compared to the reference cells. Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The worst case occurs when the output is evaluated logic high, where the pull-up networks are turned OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail. A capacitor added to the feedback path increases the node capacitance of the output and the feedback delay, thereby increasing the single event critical charge. Another differential structure that has two differential inputs and outputs eliminates single event upset issues at the expense of an increased number of transistors. Clock networks in advanced technology nodes may cause significant errors in an IC as the devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme in a digital system. It was fabricated in a 28nm technology and evaluated through the use of heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was demonstrated during these tests. In addition to mitigating single event issues by using hardened designs, built-in current sensors can be used to detect single event induced currents in the n-well and, if implemented, subsequently execute fault correction actions. These sensors were simulated and fabricated in a 28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of this sensor design. This manifests itself as an alternative to existing hardening techniques. In conclusion, this work investigates single event effects in digital systems, especially those in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock, and current sensor designs have been presented and evaluated. Through the use of these designs, the single event tolerance of a digital system can be achieved at the expense of varying overhead in terms of area, power, and delay

Sensor de corrente transiente para um sistema de proteção de circuitos integrados contra erros induzidos por radiação ionizante

Este trabalho apresenta o desenvolvimento de um sensor de corrente transiente destinado a detectar a ocorrência de um evento transiente causado pela incidência de radiação ionizante em um circuito integrado. Iniciando com uma descrição dos efeitos da radiação sobre os circuitos integrados e dos tipos de radiação de interesse, os fundamentos da técnica Bulk- BICS são apresentados e as propostas existentes na literatura são expostas e avaliadas, com ênfase no sensor que utiliza a célula de memória dinâmica DynBICS, resultado de um trabalho prévio e do qual se dispõe de amostras fabricadas. Sobre essas amostras são efetuados testes elétricos, um ensaio de dose total irradiada TID e um ensaio de estimulação laser, cujos resultados são apresentados e confirmam a funcionalidade da topologia da célula de memória dinâmica aplicada a circuitos Bulk-BICS. Em seguida, é apresentada a topologia da célula de memória integrativa como uma evolução da célula de memória dinâmica e propõe-se o circuito de um novo sensor Bulk-BICS baseado na nova célula. O funcionamento elétrico do circuito desse novo sensor TRIBICS é avaliado através de simulação de circuitos determinando-se a sensibilidade e o tempo de resposta do sensor utilizando-se pulsos de corrente em dupla exponencial. É feita uma análise do funcionamento da célula de memória estática e, através de uma comparação de desempenho entre as células de memória estáticas utilizadas em três circuitos propostos e a célula de memória integrativa, utilizando um modelo simplificado, mostra-se que a célula de memória integrativa é mais rápida e sensível do que as contrapartes estáticas O sensor TRIBICS é então simulado em conexão com um modelo de dispositivo, sendo antes apresentados os modelos TCAD do inversor utilizado como alvo da incidência da radiação nas simulações. São apresentados resultados obtidos individualmente para o transistor NMOS e para o transistor PMOS, nos quais se mostra a formação de um canal condutivo entre dreno e fonte durante o SET. Mostra-se, também, que os resultados obtidos com a simulação de dispositivos não concorda com aqueles proporcionados pela simulação de circuitos no tocante à divisão das correntes transitórias entre dreno, fonte e substrato. O resultado das simulações de dispositivo efetuadas com os modelos TCAD em modo misto com o circuito TRIBICS descrito em SPICE mostram a relação entre a transferência de energia da irradiação LET e a efetiva deteção do SET provocado, em função da distância entre os contatos de bulk ou substrato, permitindo determinar a máxima distância entre contatos para 100% de certeza na deteção do SET. Com isso, obtém-se uma estimativa do número de transistores que pode ser monitorado pelos Bulk-BICS. É proposta a estratégia de implementação dos Bulk-BICS na forma de uma standard cell a ser posicionada entre os grupos de transistores sob monitoração, e uma estimativa da relação entre as áreas dos transistores monitorados e do Bulk-BICS é apresentada. Por fim, é estudada a questão da fabricação dos Bulk-BICS no mesmo substrato dos transistores monitorados e uma maneira de fazê-la é proposta. Os resultados encontrados permitem definir a viabilidade e a eficácia da técnica Bulk-BICS como forma de deteção de eventos transientes em sistemas digitais.A current sensor to detect the occurrence of a single-event transient that is caused by the incidence of ionizing radiation in an integrated circuit is presented. Radiation of interest and their effects on the integrated circuits are discussed. Fundamentals of the Bulk-BICS technique and the circuits proposed in the literature to implement this technique are discussed and evaluated, with emphasis on the dynamic memory cell-based circuit DynBICS, which was developed as a previous work and with fabricated samples available. Experimental results obtained from a series of electrical tests, a TID test, and a laser-stimulated test that were conducted on a number of fabricated and packaged samples are presented. The results confirm that the dynamic memory cell is suitable and robust enough to be used in Bulk-BICS circuits. Next, evolution of the dynamic memory cell into an integrative memory cell is discussed and the circuit of a Bulk-BICS using this new memory cell topology is presented. The electrical operation of this new sensor TRIBICS is evaluated using circuit simulations. By using double-exponential current pulses, both the sensitivity and the response time are determined. The static memory cell operation is analyzed and a comparison of performance between static and integrative cells is performed using a simplified model. The results show that the integrative memory cell is faster and more sensitive than the static cells used in three state-ofthe- art sensors published in literature Then the TRIBICS sensor is simulated connected to a TCAD-modeled device, comprising an inverter, which is used as a target for radiation impact. TCAD models are previously presented and the results obtained when the PMOS and NMOS transistors are separately excited by radiation show the formation of a conductive link between drain and source regions during the occurrence of SET. The simulations also show that the results obtained by using TCAD simulations do not agree with the ones obtained by using circuit simulation regarding the current share among drain, source and bulk during the SET. Mixed-mode simulations using the TCAD models in conjunction of TRIBICS circuits described in SPICE show the relationship between LET and the effective SET-detection with the inter-tap distance as a parameter, and allows to determine the inter-tap distance for 100% of SET detection efficiency. Based on these results, an estimate of how many transistors can be monitored by the Bulk-BICS is obtained. It is proposed to implement the Bulk-BICS as a standard cell, to be positioned in between the standard cell that compose a digital circuit and the area overhead necessary to implant the sensors in a real circuit is estimated. The problem on how to manufacture the Bulk-BICS circuit in the same substrate of the monitored transistors is studied and a solution is proposed. The results show the viability and effectiveness of the Bulk-BICS technique, as a means to detect single-event transients in digital systems