3 research outputs found
On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks
High-level synthesis (HLS) tools have provided significant productivity
enhancements to the design flow of digital systems in recent years, resulting
in highly-optimized circuits, in terms of area and latency. Given the evolution
of hardware attacks, which can render them vulnerable, it is essential to
consider security as a significant aspect of the HLS design flow. Yet the need
to evaluate a huge number of functionally equivalent de-signs of the HLS design
space challenges hardware security evaluation methods (e.g., fault injection -
FI campaigns). In this work, we propose an evaluation methodology of hardware
security properties of HLS-produced designs using state-of-the-art Graph Neural
Network (GNN) approaches that achieves significant speedup and better
scalability than typical evaluation methods (such as FI). We demonstrate the
proposed methodology on a Double Modular Redundancy (DMR) coun-termeasure
applied on an AES SBox implementation, en-hanced by diversifying the redundant
modules through HLS directives. The experimental results show that GNNs can be
efficiently trained to predict important hardware security met-rics concerning
fault attacks (e.g., critical and detection error rates), by using regression.
The proposed method predicts the fault vulnerability metrics of the HLS-based
designs with high R-squared scores and achieves huge speedup compared to fault
injection once the training of the GNN is completed.Comment: 6 pages, 2 figures, 3 tables, submitted to 2023 IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
(DFT
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks
International audienceLaser attacks, especially on circuits manufactured with recent deep submicron semiconductor technologies, pose a threat to secure integrated circuits due to the multiplicity of errors induced by a single attack. An efficient way to neutralize such effects is the design of appropriate countermeasures, according to the circuit implementation and characteristics. Therefore tools which allow the early evaluation of security implementations are necessary. Our efforts involve the development of an RTL fault injection approach more representative of laser attacks than random multi-bit fault injections and the utilization and evolution of state of the art emulation techniques to reduce the duration of the fault injection campaigns. This will ultimately lead to the design and validation of new countermeasures against laser attacks, on ASICs implementing cryptographic algorithms