A survey of design techniques for system-level dynamic power management

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware component

A method of redundant clocking detection and power reduction at RT level design

This paper proposes a novel method to estimate and to re-duce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redun-dant clockings which activate registers unnecessarily, we de-tect these clockings. They are detected from the difference of the numbers of incoming and outgoing data of a regis-ter. And then we introduce gated-clock scheme to reduce the power consumption of the circuits using our estimation re-sults. Experimental results demonstrate the accuracy of our method and the effect on power reduction.