An ultra-low-power voltage-mode asynchronous WTA-LTA circuit

This paper presents an asynchronous mixed-signal WTA-LTA circuit conceived to carry out local minimummaximum indexing in massively parallel image processing arrays. The hardware is focused on energy-efficient operation. We describe a realization for the standard CMOS base process of a commercial 3-D TSV stack featuring a power consumption of only 20pW per elementary cell at 30fps. The proposed block is also capable of resolving small voltage differences without requiring any external reference. This leads to a hit percentage greater than 90% even when taking into account global process variations and mismatch conditions.MINECO TEC2012-38921-C02-01Fondo Europeo de Desarrollo Regional IPT-2011-1625- 430000 IPC-2011100

A Low-Power, High-Resolution WTA Utilizing Translinear-Loop Pre-Amplifier

[[abstract]]This paper proposes a low-power, high-resolution Winner-Take-All (WTA) circuit basing on transistors in subthreshold operation. The WTA adapts a tree structure to reduce the effect of process variations. In addition to the traditional way of using positive feedback to improve the comparison performance, we propose to use translinear loop to amplify the difference between two inputs before comparison to achieve high resolution. The circuit has been fabricated with TSMC 0.35μm 2P4M process. The WTA operates with input current as low as a few nano amperes and resolution as high as 0.1%. Measurement results show that the circuit has a non-negligible offset. Discussions on the source of the offset with a proposed solution are also given.[[fileno]]2030141030017[[department]]電機工程學

Configurable Low Power Analog Multilayer Perceptron

A configurable, low power analog implementation of a multilayer perceptron (MLP) is presented in this work. It features a highly programmable system that allows the user to create a MLP neural network design of their choosing. In addition to the configurability, this neural network provides the ability of low power operation via analog circuitry in its neurons. The main MLP system is made up of 12 neurons that can be configurable to any number of layers and neurons per layer until all available resources are utilized. The MLP network is fabricated in a standard 0.13 μm CMOS process occupying approximately 1 mm2 of on-chip area. The MLP system is analyzed at several different configurations with all achieving a greater than 1 Tera-operations per second per Watt figure of merit. This work offers a high speed, low power, and scalable alternative to digital configurable neural networks