Design of High Speed Comparator

A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog - to - digital converters with High Spee d, low power dissipation and immune to. Back - to - back inverter in the latch stage is replaced with dual - input single output differential amplifier. This topology completely removes the noise that is present in the input. The stru cture shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current source ces, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, n oise immunity

Design of a novel high speed dynamic comparator with low power dissipation for high speed ADCs

A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Backto- back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in Cadence® Virtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established

Pixel and Readout Circuit of a Wide Dynamic Range Linear-Logarithmic Current-Mode Image Sensor

RESUME Le capteur d’images est la partie principale de tout système d’acquisition d’images, quelle que soit son application. Jusqu’à la fin des années 1990, les capteurs de type CCD ont dominé le marché en raison de leur qualité d’image exceptionnelle. À l’opposé des capteurs CCD, les capteurs CMOS offrent des possibilités intéressantes d’intégrer les circuits de traitement de signal sur un même substrat en vue d’obtenir une caméra sur puce. Entant que ces capteurs opèrent avec des tensions d’alimentations plus faibles que celles requise par les capteurs CCD, elles possèdent une faible consommation de puissance. De plus, les coûts associés à la fabrication des capteurs CMOS sont plus faibles que ceux engendrés par les capteurs CCD. Ces caractéristiques font en sorte que les capteurs d’images CMOS se prêtent à un plus grand nombre d’application que leurs équivalents CCD. Dans ce projet, l’objectif principal est de concevoir un capteur d’images ayant une plage dynamique élevée. Il possède l’avantage de deux modes d’opération, linéaire et logarithmique, ainsi qu’une lecture en mode courant afin d’augmenter sa plage dynamique. Les tensions d’alimentation des technologies CMOS diminue de plus en plus, et de ce fait la plage dynamique du pixel. En fonctionnant en mode courant, on arrive à atténuer cet effet. Le projet consiste à concevoir des circuits : convoyeur de courant, ‘delta-reset-sampling’ et un comparateur de courant qui sont efficaces pour les modes d’opération linéaire et logarithmique du pixel et permettent de détecter dans quels des deux modes se situe le pixel de façon à réaliser, à l’étage subséquent, une conversion analogique-numérique adéquate. Le pixel à trois transistors fonctionnant en mode courant utilise un transistor PMOS dans la région linéaire pour la lecture et un transistor PMOS de reset qui permet une réponse linéaire-logarithmique combinée. L'une des contributions à la non-linéarité de la réponse provient de l'effet provoqué par la résistance ‘on’ du transistor ‘select’. Pour éliminer cet effet, nous appliquons une fonction de linéarisation qui est effectuée dans le domaine numérique. Le mode d’opération du pixel est déterminé dans le circuit de lecture de colonne et un signal est envoyé à l'unité de traitement numérique comme indicateur de mode. Un prototype a été conçu et fabriqué en CMOS 0.35µm standard, 3.3V. Les résultats expérimentaux sont concluants et montrent une plage dynamique intrascènede 100 dB.----------ABSTRACT Digital cameras are rapidly becoming a dominant image capture devices. They are enabling many new applications. Charge-coupled devices (CCDs) have been the basis for solid state imaging since the 1970s. However, during the last decade, interest in CMOS imagers has increased significantly since they are capable of offering System-on-Chip (SoC) functionality. This can greatly reduce camera cost, power consumption, and size. Furthermore, by integrating innovative circuits on the same chip, the performance of CMOS image sensors could be extended beyond the capabilities of CCDs. Dynamic range is an important performance criterion for all image sensors. This thesis presents a current-mode CMOS image sensor operating in linear-logarithmic response. The objective of this design is to improve the dynamic range of the image sensor, and to provide a method for mode detection of the image sensor response. One of the motivations of using current-mode has been the shrinking feature size of CMOS devices. This leads to the reduction of supply voltage which causes the degradation of circuit performance in term of dynamic range. Such problem can be alleviated by operating in current-mode. The column readout circuits are designed in current-mode in order to be compatible with the image sensor. The readout circuit is composed of a first-generation current conveyor, an improved current memory is employed as a delta reset sampling unit, a differential amplifier as an integrator and a dynamic comparator. The current-mode three-transistor active pixel sensor uses a PMOS readout transistor in the linear region of operation and a PMOS reset transistor that allows for a linear-logarithmic response. One of the non-linearity contributions is the effect caused by the ‘on’ resistance of the select transistor. To eliminate this effect, we apply a linearization function that can be performed in the digital domain. The pixel response operation is determined in the column readout circuit and a signal is sent to the digital processing unit as an indicator. These circuits were implemented using a standard CMOS technology with no process modification. A prototype has been designed and fabricated in a standard AMS 2P4M, 3.3V, CMOS 0.35μm process from Austrian Microsystem

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration