Evaluation of Temporal readout noise in low power CMOS Sensors

Our research currently focusing on image sensors predominantly the sensors implemented using CMOS (Complementary Metal Oxide Semiconductor) technology. These sensors designated as CMOS sensors which were introduced after CCD (Charge-coupled Devices) sensors since CCDs having some drawbacks in terms of its power and making cost compared to CMOS sensors. The most prominent feature of the CMOS sensors is that they can work at low voltage. CMOS sensors need only one supply voltage but CCDs require three to four which makes the cost of the CMOS sensor very low compared to CCD. CMOS image sensors in general have higher temporal noise, higher fixed pattern noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range (DR) and superior signal to noise ratio (SNR) that the CCD image sensors have. The Temporal noise of low power CMOS Sensor is evaluated with respect to various pixel sizes and Pixel arrays and corresponding regression analysis applied to obtain the linearity between the input voltage and the power consumed by the sensor in different technical environments

Hybrid Amorphous-Selenium/CMOS Low-Light Imager

This thesis aims to demonstrate a low-light imager capable of moonlight-level imag- ing by combining a custom-designed complementary-metal-oxide-semiconductor (CMOS) pixel array with amorphous selenium (a-Se) as its photosensor. Because of the low dark current of a-Se compared to standard silicon photodiodes, this hybrid structure could enable imagers fabricated in standard mixed-signal CMOS processes to achieve low- light imaging. Such hybrid imagers could have low-light performances comparable to other low-light imagers fabricated in specialized CMOS image-sensor processes. The 320 (H) x 240 (V) imager contains four different pixel designs arranged in four quadrants, with pixel pitches of 7.76 μm x 7.76 μm in quadrants 1 to 3 and 7.76 μm x 8.66 μm in quadrant 4 (Q4). The different quadrants are built to examine various performance-enhancing circuit designs and techniques, including series-stacked devices for leakage suppression, charge-injection suppression that uses dummy transistors, and a programmable dual-capacity design for extended pixel dynamic range. The imager- performance parameters, such as noise, dynamic range, conversion gain, linearity, and full-well capacity were simulated and experimentally verified. This work will also de- scribe the external hardware and software designs used to operate the imager. This thesis summarizes and reports the overall electrical and optical performance of pixels in quadrant 1. The observed signal-to-noise ratio (SNR) of above 20 dB at an illuminance of 0.267 lux demonstrates that the imager can produce excellent images under moonlight-imaging conditions. This was achieved mainly through utilization of the long integration time enabled by circuit techniques implemented at the pixel level, as well as the low dark current of a-Se

Ultra Low Noise CMOS Image Sensors

CMOS Image Sensors (CIS) overtook the charge coupled devices (CCDs) in low noise performance. Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. This work presents a review of CMOS image sensors based on pinned photo diodes (PPDs). The latter includes the historical background, the PPD physics and the readout chain circuits used for low-noise performance. The physical mechanisms behind the random fluctuations affecting the signal at different levels of conventional CIS readout chains are reviewed and clarified. This thesis dedicates a particular focus to the readout circuit noise given that it precludes photoelectron counting in conventional CIS. A detailed analytical calculation of the temporal read noise (TRN) in conventional CIS readout chain is presented. The latter suggests different noise reduction techniques at process and circuit design level. Among the noise reduction techniques suggested by the analytical noise calculation, the increase of the oxide capacitance by using a thin oxide in-pixel amplifying transistor, for low 1/f noise, is suggested for the first time. A test chip designed in a 180 nm CIS process and embedding optimized readout chains exploiting the new pixels together with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 e-rms has been measured. Compared with the state-of-the-art pixels, also present onto the test chip, the mean RMS noise is divided by more than 2. Based on these encouraging result, a full VGA (640H×480V) imager has been integrated in a standard CIS process. The presented imager relies on a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. The sensor chip features an input-referred noise histogram from 0.25 e-rms to a few e-rms peaking at 0.48 e-rms. This sub-0.5 electron noise performance is obtained with a full well capacity of 6400 e- and a frame rate that can go up to 80 fps. The VGA imager also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e-/s. Correlated multiple sampling (CMS) is a noise reduction technique commonly used in low noise CIS. This work presents an original design for CMS based on a passive switched-capacitor network, with a minimum number of capacitors. The proposed circuit requires no additional active circuitry, has no impact on the output dynamic range and does not need multiple analog-to-digital conversions. It was verified with transient noise simulations and shows a noise reduction in perfect agreement with ideal CMS. For a future perspective, the impact of the technology downscale on CIS sensitivity from an electronic read noise aspect is investigated. Active imaging in the Terahertz (THz) band is an emerging technology. Source modulation combined with a selective filtering can be used to reduce the noise in CMOS THz imagers. This work presents the first integration of a 1 kpixel CMOS THz imager integrating, in each pixel, a metal antenna with a MOS rectifier, low noise amplification and highly selective filtering, based on a switch-capacitor N-path filter combined with a broad band Gm-C filter. The latter has been tested successfully. An input-referred noise of 0.2 µV RMS corresponding to a total noise equivalent THz power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz