Thermoelectric Cooling to Survive Commodity DRAMs in Harsh Environment Automotive Electronics

Today, more and more commodity hardware devices are used in safety-critical applications, such as advanced driver assistance systems in automotive. These applications demand very high reliability of electronic components even in adverse environmental conditions, such as high temperatures. Ensuring the reliability of microelectronic components is a major challenge at these high temperatures. The computing systems of these applications rely on DRAMs as working memory, which are built upon bit cells that store charges in capacitors. These commodity DRAMs are optimized for cost per bit and not for high reliability. Thus, very high temperatures impose an enormous challenge for commodity DRAMs as the data retention time and reliability decrease largely, affecting the data correctness. Data correctness can be ensured up to certain temperatures by increasing the refresh rate to counterbalance the retention time reduction. However, this severely degrades the access latencies and the usable DRAM bandwidth. To overcome these limitations, we present for the first time a Thermoelectric Cooling (TEC) solution for commodity DRAMs in harsh-environments, such as automotive. Our TEC solution enables the use of commodity off-the-shelf DRAMs in safety-critical applications by reducing the temperature conditions to a range where they can operate reliably. This TEC solution is applied a posteriori to the DRAM chips without using high-cost package solutions. Thus, it maintains the low-cost targets of such devices, improves the reliability, and at the same time, counterbalances the adverse effects of increasing the refresh rate. To quantitatively evaluate the benefits of TEC on commodity DRAMs in harsh-environments, we performed system-level evaluations with several applications backed up by the measured data on commodity DRAMs. Our experimental results, using accurate multi-physics simulations that employ finite element method, demonstrate that the TEC-based cooling ensures that the maxim..

펄스 기반 피드 포워드 이퀄라이저를 갖춘 고용량 DRAM을 위한 컨트롤러 PHY 설계

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 김수환.A controller PHY for managed DRAM solution, which is a new memory structure to maximize capacity while minimizing refresh power, is presented. Inter-symbol interference is critical in such a high-capacity DRAM interface in which many DRAM chips share a command/address (C/A) channel. A pulse-based feed-forward equalizer (PB-FFE) is introduced to reduce ISI on a C/A channel. The controller PHY supports all the training sequences specified in the DDR4 standard. A glitch-free DCDL is also adopted to perform link training efficiently and to reduce training time. The DQ transmitter adopts quarter-rate architecture to reduce output latency. For the quarter-rate transmitters in DQ, we propose a quadrature error corrector (QEC), in which clock signal phase errors are corrected using two replicas of the 4:1 serializer of the output stage. Pulse shrinking is used to compare and equalize the outputs of these two replica serializers. A controller PHY was fabricated in 55nm CMOS. The PB-FFE increases the timing margin from 0.23UI to 0.29UI at 1067Mbps. At 2133Mbps, the read timing and voltage margins are 0.53UI and 211mV after read training, and the write margins are 0.72UI and 230mV after write training. To validate the QEC effectiveness, a prototype quarter-rate transmitter, including the QEC, was fabricated to another chip in 65nm CMOS. Adopting our QEC, the experimental results show that the output phase errors of the transmitter are reduced to a residual error of 0.8ps, and the output eye width and height are improved by 84% and 61%, respectively, at a data-rate of 12.8Gbps.본 연구에서 용량을 최대화하면서도 리프레시 전력을 최소화할 수 있는 새로운 메모리 구조인 관리형 DRAM 솔루션을 위한 컨트롤러 PHY를 제시하였다. 이와 같은 고용량 DRAM 인터페이스에서는 많은 DRAM 칩이 명령 / 주소 (C/A) 채널을 공유하고 있어서 심볼 간 간섭이 발생한다. 본 연구에서는 이러한 C/A 채널에서의 심볼 간 간섭을 줄이기 위해 펄스 기반 피드 포워드 이퀄라이저 (PB-FFE)를 채택하였다. 또한 본 연구의 컨트롤러 PHY는 DDR4 표준에 지정된 모든 트레이닝 시퀀스를 지원한다. 링크 트레이닝을 효율적으로 수행하고 트레이닝 시간을 줄이기 위해 글리치가 발생하지 않는 디지털 제어 지연 라인 (DCDL)을 채택하였다. 컨트롤러 PHY의 DQ 송신기는 출력 대기 시간을 줄이기 위해 쿼터 레이트 구조를 채택하였다. 쿼터 레이트 송신기의 경우에는 직교 클럭 간 위상 오류가 출력 신호의 무결성에 영향을 주게 된다. 이러한 영향을 최소화하기 위해 본 연구에서는 출력 단의 4 : 1 직렬 변환기의 두 복제본을 사용하여 클록 신호 위상 오류를 수정하는 QEC (Quadrature Error Corrector)를 제안하였다. 복제된 2개의 직렬 변환기의 출력을 비교하고 균등화하기 위해 펄스 수축 지연 라인이 사용되었다. 컨트롤러 PHY는 55nm CMOS 공정으로 제조되었다. PB-FFE는 1067Mbps에서 C/A 채널 타이밍 마진을 0.23UI에서 0.29UI로 증가시킨다. 읽기 트레이닝 후 읽기 타이밍 및 전압 마진은 2133Mbps에서 0.53UI 및 211mV이고, 쓰기 트레이닝 후 쓰기 마진은 0.72UI 및 230mV이다. QEC의 효과를 검증하기 위해 QEC를 포함한 프로토 타입 쿼터 레이트 송신기를 65nm CMOS의 다른 칩으로 제작하였다. QEC를 적용한 실험 결과, 송신기의 출력 위상 오류가 0.8ps의 잔류 오류로 감소하고, 출력 데이터 눈의 폭과 높이가 12.8Gbps의 데이터 속도에서 각각 84 %와 61 % 개선되었음을 보여준다.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.1.1 HEAVY LOAD C/A CHANNEL 5 1.1.2 QUARTER-RATE ARCHITECTURE IN DQ TRANSMITTER 7 1.1.3 SUMMARY 8 1.2 THESIS ORGANIZATION 10 CHAPTER 2 ARCHITECTURE 11 2.1 MDS DIMM STRUCTURE 11 2.2 MDS CONTROLLER 15 2.3 MDS CONTROLLER PHY 17 2.3.1 INITIALIZATION SEQUENCE 20 2.3.2 LINK TRAINING FINITE-STATE MACHINE 23 2.3.3 POWER DOWN MODE 28 CHAPTER 3 PULSE-BASED FEED-FORWARD EQUALIZER 29 3.1 COMMAND/ADDRESS CHANNEL 29 3.2 COMMAND/ADDRESS TRANSMITTER 33 3.3 PULSE-BASED FEED-FORWARD EQUALIZER 35 CHAPTER 4 CIRCUIT IMPLEMENTATION 39 4.1 BUILDING BLOCKS 39 4.1.1 ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL) 39 4.1.2 ALL-DIGITAL DELAY-LOCKED LOOP (ADDLL) 44 4.1.3 GLITCH-FREE DCDL CONTROL 47 4.1.4 DUTY-CYCLE CORRECTOR (DCC) 50 4.1.5 DQ/DQS TRANSMITTER 52 4.1.6 DQ/DQS RECEIVER 54 4.1.7 ZQ CALIBRATION 56 4.2 MODELING AND VERIFICATION OF LINK TRAINING 59 4.3 BUILT-IN SELF-TEST CIRCUITS 66 CHAPTER 5 QUADRATURE ERROR CORRECTOR USING REPLICA SERIALIZERS AND PULSE-SHRINKING DELAY LINES 69 5.1 PHASE CORRECTION USING REPLICA SERIALIZERS AND PULSE-SHRINKING UNITS 69 5.2 OVERALL QEC ARCHITECTURE AND ITS OPERATION 71 5.3 FINE DELAY UNIT IN THE PSDL 76 CHAPTER 6 EXPERIMENTAL RESULTS 78 6.1 CONTROLLER PHY 78 6.2 PROTOTYPE QEC 88 CHAPTER 7 CONCLUSION 94 BIBLIOGRAPHY 96Docto

Hardware Mechanisms for Efficient Memory System Security

The security of a computer system hinges on the trustworthiness of the operating system and the hardware, as applications rely on them to protect code and data. As a result, multiple protections for safeguarding the hardware and OS from attacks are being continuously proposed and deployed. These defenses, however, are far from ideal as they only provide partial protection, require complex hardware and software stacks, or incur high overheads. This dissertation presents hardware mechanisms for efficiently providing strong protections against an array of attacks on the memory hardware and the operating system’s code and data. In the first part of this dissertation, we analyze and optimize protections targeted at defending memory hardware from physical attacks. We begin by showing that, contrary to popular belief, current DDR3 and DDR4 memory systems that employ memory scrambling are still susceptible to cold boot attacks (where the DRAM is frozen to give it sufficient retention time and is then re-read by an attacker after reboot to extract sensitive data). We then describe how memory scramblers in modern memory controllers can be transparently replaced by strong stream ciphers without impacting performance. We also demonstrate how the large storage overheads associated with authenticated memory encryption schemes (which enable tamper-proof storage in off-chip memories) can be reduced by leveraging compact integer encodings and error-correcting code (ECC) DRAMs – without forgoing the error detection and correction capabilities of ECC DRAMs. The second part of this dissertation presents Neverland: a low-overhead, hardware-assisted, memory protection scheme that safeguards the operating system from rootkits and kernel-mode malware. Once the system is done booting, Neverland’s hardware takes away the operating system’s ability to overwrite certain configuration registers, as well as portions of its own physical address space that contain kernel code and security-critical data. Furthermore, it prohibits the CPU from fetching privileged code from any memory region lying outside the physical addresses assigned to the OS kernel and drivers. This combination of protections makes it extremely hard for an attacker to tamper with the kernel or introduce new privileged code into the system – even in the presence of software vulnerabilities. Neverland enables operating systems to reduce their attack surface without having to rely on complex integrity monitoring software or hardware. The hardware mechanisms we present in this dissertation provide building blocks for constructing a secure computing base while incurring lower overheads than existing protections.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147604/1/salessaf_1.pd

PAM4-바이너리 브리지 칩용 PAM4 트랜스미터 설계

학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 정덕균.고성능 컴퓨팅 시스템, 대용량의 데이터 센터, AI 기술의 발전으로 인해 유선 통신의 대역폭 요구 수준은 기하급수적으로 증가하고 있다. 그러나 I/O 회로의 핀당 대역폭의 향상은 통신 채널의 다양한 한계로 인해 어려움을 겪고 있다. 이는 차세대 DRAM 분야에서도 예외는 아니다. 핀당 데이터 전송 속도를 증가시키는 연구 방향에서는 어느 정도 한계에 봉착하면서 최근에는 High Bandwidth Memory (HBM)와 같이 핀의 개수를 급격히 늘려서 대역폭을 증가시키는 기술도 발전하고 있다. 다른 접근 방식 중 한가지가 다중 레벨 신호 방식이다. 기존의 Non-Return-to-Zero (NRZ) 신호 대신에 다중 레벨 신호 방식을 이용하면 동일한 Nyquist 주파수에서 데이터 속도를 높일 수 있고 이는 DRAM의 차세대 고대역폭 I/O 인터페이스에 좋은 솔루션이 될 수 있으며 현재까지는 4레벨 펄스 진폭 변조 방식 (PAM-4)이 널리 채택되어 있다. 하지만 현재 PAM-4 방식 DRAM이 양산 단계가 아니기 때문에 PAM-4 전용 Memory Tester가 없는 상황이다. 본 논문에서는 차세대 메모리 테스트를 위한 32 Gb/s PAM4 바이너리 브리지에서의 트랜스미터를 제안한다. NRZ 테스터에서 브리지로 전송된 저속 데이터는 고속 PAM4 데이터로 변환되어 메모리로 전달된다. 접지 종단 PAM4 드라이버는 2-탭 피드포워드 이퀄라이저로 출력 전류를 제어하여 0.95의 레벨 불일치 비율 (RLM)을 달성함으로써 단일 종단 출력을 제공한다. 40 nm CMOS 기술로 제작된 브리지 트랜스미터는 0.57 mm2의 활성 영역을 차지하고 102.1 mW의 전력을 소모한다.With the advancement of high-performance computing systems, large-capacity data centers, and AI technologies, the level of bandwidth demand for wired communication is increasing exponentially. However, the improvement of the bandwidth per pin in the I/O circuit compared to the required bandwidth level is difficult due to various limitations of the transmission channel. This is no exception in the next generation of DRAM. While facing limitations from the perspective of research that increases data transmission speed per pin, technologies that increase I/O bandwidth by rapidly increasing the number of pins, such as High Bandwidth Memory (HBM), have also recently developed. One of the other approaches is a multi-level signaling method. Using a multi-level signaling method instead of a conventional Non-Return-to-Zero (NRZ) signal can increase data speed at the same Nyquist frequency, which can be a good solution for the next-generation high-bandwidth I/O interface of DRAM, and so far, a four-level Pulse Amplitude Modulation (PAM-4) has been widely adopted. However, since PAM4 DRAM is not in the mass production stage yet, there is no memory tester dedicated to PAM4 signaling. This paper proposes a transmitter block on a 32 Gb/s PAM4 binary bridge for next-generation memory testing. The low-speed data transmitted from the NRZ tester to the bridge is converted into high-speed PAM4 data through half-rate clock control and transferred to the memory. The ground termination PAM4 driver provides a single-ended output by controlling the output current with a two-tap feed forward equalizer to achieve a Level separation Mismatch Ratio (RLM) of 0.95. Bridge transmitter manufactured with 40 nm CMOS technology occupies an active area of 0.57 mm2 and consumes 102.1 mW of power.ABSTRACT I CONTENTS Ⅲ LIST OF FIGURES Ⅴ LIST OF TABLES Ⅶ CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 CHAPTER 2 BACKGROUNDS 5 2.1 OVERVIEW 5 2.2 BASIC OF MULTI LEVEL SIGNALING 7 2.3 NECESSITY OF PAM4-BINARY BRIDGE 11 CHAPTER 3 DESIGN OF PAM4 TRANSMITTER FOR PAM4-BINARY BRIDGE 14 3.1 DESIGN CONSIDERATION 14 3.2 OVERALL ARCHITECTURE 17 3.3 CIRCUIT IMPLEMENTATION 19 3.3.1 CLOCK GENERATOR 19 3.3.2 PARALLEL PRBS GENERATOR 23 3.3.3 DATA ALIGN / GRAY CODE ENDCODER 26 3.3.4 FFE CONTROL/ SERIALIZER 30 3.3.5 PAM4 DRIVER 33 CHAPTER 4 MEASUREMENT RESULTS 38 4.1 CHIP PHOTOMICROGRAPH 38 4.2 MEASUREMENT SETUP 39 4.3 MEASUREMENT RESULTS 40 4.4 PERFORMANCE SUMMARY 42 CHAPTER 5 CONCLUSION 46 BIBLIOGRAPHY 47 초 록 50석