A Component-Based Middleware for a Reliable Distributed and Reconfigurable Spacecraft Onboard Computer

Emerging applications for space missions require increasing processing performance from the onboard computers. DLR's project “Onboard Computer - Next Generation” (OBC-NG) develops a distributed, reconfigurable computer architecture to provide increased performance while maintaining the high reliability of classical spacecraft computer architectures. Growing system complexity requires an advanced onboard middleware, handling distributed (realtime) applications and error mitigation by reconfiguration. The OBC-NG middleware follows the Component-Based Software Engineering (CBSE) approach. Using composite components, applications and management tasks can easily be distributed and relocated on the processing nodes of the network. Additionally, reuse of components for future missions is facilitated. This paper presents the flexible middleware architecture, the composite component framework, the middleware services and the model-driven Application Programming Interface (API) design of OBC-NG. Tests are conducted to validate the middleware concept and to investigate the reconfiguration efficiency as well as the reliability of the system. A relevant use case shows the advantages of CBSE for the development of distributed reconfigurable onboard software

Method and system for environmentally adaptive fault tolerant computing

A method and system for adapting fault tolerant computing. The method includes the steps of measuring an environmental condition representative of an environment. An on-board processing system's sensitivity to the measured environmental condition is measured. It is determined whether to reconfigure a fault tolerance of the on-board processing system based in part on the measured environmental condition. The fault tolerance of the on-board processing system may be reconfigured based in part on the measured environmental condition

Massively Extended Modular Monitoring and a Second Life for Upper Stages

Launching science and technology experiments to space is expensive. Although commercial spaceflight has resulted in a drop of prices, the cost for a launch is still significant. However, most of theweight that is needed to conduct experiments in space belongs to the spacecraft’s bus and it is responsiblefor power distribution, thermal management, orbital control and communications. An upper stage, on the other hand, includes all the necessary subsystems andhas to be launched in any case. Many upper stages (e.g. ARIANE5) will even stay in orbit for severalyears after their nominal mission with all their subsystems intact but passivated.We proposea compact system based on a protective container and high-performance Commercial-off-the-Shelf (COTS) hardwarethat allows cost-efficient launching oftechnology experiments by reusing the launcher’s upper stage and its subsystems. Addingacquisition channels for various sensors gives the launch provider the ability to exploitthe computational power of the COTS hardwareduring the nominal mission. In contrast to existing systems,intelligent and mission-dependent data selection and compression can beapplied to the sensor data.In this paper, we demonstrate the implementation and qualification of a payload bussystem based on COTScomponentsthat is minimallyinvasive to the launcher(ARIANE5)and its nominal missionwhile offering computational power to both the launch provider and a potential payloaduser. The reliability of the COTS-based system is improvedby radiation hardening techniques and software-based self-test detecting and counteracting faults during the mission

Design an Object-Oriented Home Inspection Application for a Portable Device

Recent advancements in the personal digital assistant (PDA) Windows application programming methodology made it easier to develop PDA applications. The release of the Microsoft® Visual Studio 2005 .NET incorporated handheld programming support while the Microsoft® Mobile® 5.0 operating system dramatically improved the PDA\u27s operation and hardware configuration. This paper researches and analyzes object-oriented languages, relational database and dynamic report generation technologies for the PDA as they apply to the development of a professional home inspection application. The focus of this paper is on the implementation of the most advanced PDA technologies for a high-end database PDA application design

A Touch of Evil: High-Assurance Cryptographic Hardware from Untrusted Components

The semiconductor industry is fully globalized and integrated circuits (ICs) are commonly defined, designed and fabricated in different premises across the world. This reduces production costs, but also exposes ICs to supply chain attacks, where insiders introduce malicious circuitry into the final products. Additionally, despite extensive post-fabrication testing, it is not uncommon for ICs with subtle fabrication errors to make it into production systems. While many systems may be able to tolerate a few byzantine components, this is not the case for cryptographic hardware, storing and computing on confidential data. For this reason, many error and backdoor detection techniques have been proposed over the years. So far all attempts have been either quickly circumvented, or come with unrealistically high manufacturing costs and complexity. This paper proposes Myst, a practical high-assurance architecture, that uses commercial off-the-shelf (COTS) hardware, and provides strong security guarantees, even in the presence of multiple malicious or faulty components. The key idea is to combine protective-redundancy with modern threshold cryptographic techniques to build a system tolerant to hardware trojans and errors. To evaluate our design, we build a Hardware Security Module that provides the highest level of assurance possible with COTS components. Specifically, we employ more than a hundred COTS secure crypto-coprocessors, verified to FIPS140-2 Level 4 tamper-resistance standards, and use them to realize high-confidentiality random number generation, key derivation, public key decryption and signing. Our experiments show a reasonable computational overhead (less than 1% for both Decryption and Signing) and an exponential increase in backdoor-tolerance as more ICs are added

Pushing the Boundaries of Spacecraft Autonomy and Resilience with a Custom Software Framework and Onboard Digital Twin

This research addresses the high CubeSat mission failure rates caused by inadequate software and overreliance on ground control. By applying a reliable design methodology to flight software development and developing an onboard digital twin platform with fault prediction capabilities, this study provides a solution to increase satellite resilience and autonomy, thus reducing the risk of mission failure. These findings have implications for spacecraft of all sizes, paving the way for more resilient space missions

High-Performance Computing for SKA Transient Search: Use of FPGA based Accelerators -- a brief review

This paper presents the High-Performance computing efforts with FPGA for the accelerated pulsar/transient search for the SKA. Case studies are presented from within SKA and pathfinder telescopes highlighting future opportunities. It reviews the scenario that has shifted from offline processing of the radio telescope data to digitizing several hundreds/thousands of antenna outputs over huge bandwidths, forming several 100s of beams, and processing the data in the SKA real-time pulsar search pipelines. A brief account of the different architectures of the accelerators, primarily the new generation Field Programmable Gate Array-based accelerators, showing their critical roles to achieve high-performance computing and in handling the enormous data volume problems of the SKA is presented here. It also presents the power-performance efficiency of this emerging technology and presents potential future scenarios.Comment: Accepted for JoAA, SKA Special issue on SKA (2022

System Architecture of Small Unmanned Aerial System for Flight beyond Visual Line-Of-Sight

Small Unmanned Aerial Systems (UAS) have increasingly been used in military application. The application in expanding scope of operations has pushed existing small UAS beyond its designed capabilities. This resulted in frequent modifications or new designs. A common requirement in modification or new design of small UAS is to operate beyond visual Line-Of-Sight (LOS) of the ground pilot. Conventional military development for small UAS adopts a design and built approach. Modification of small Remote Control (RC) aircraft, using Commercial-Off-The Shelf (COTS) equipment, offers a more economical alternative with the prospect of shorter development time compared to conventional approach. This research seeks to establish and demonstrate an architecture framework and design a prototype small UAS for operation beyond visual LOS. The aim is to achieve an effective and reliable development approach that is relevant to the military’s evolving requirements for small UASs. Key elements of the architecture include Failure Mode Effect and Criticality Analysis (FMECA), fail safe design for loss of control or communication, power management, interface definition, and configuration control to support varying onboard payloads. Flight test was conducted which successfully demonstrated a control handoff between local and remote Ground Station (GS) for beyond visual LOS operation

Operating System Support for Redundant Multithreading

Failing hardware is a fact and trends in microprocessor design indicate that the fraction of hardware suffering from permanent and transient faults will continue to increase in future chip generations. Researchers proposed various solutions to this issue with different downsides: Specialized hardware components make hardware more expensive in production and consume additional energy at runtime. Fault-tolerant algorithms and libraries enforce specific programming models on the developer. Compiler-based fault tolerance requires the source code for all applications to be available for recompilation. In this thesis I present ASTEROID, an operating system architecture that integrates applications with different reliability needs. ASTEROID is built on top of the L4/Fiasco.OC microkernel and extends the system with Romain, an operating system service that transparently replicates user applications. Romain supports single- and multi-threaded applications without requiring access to the application's source code. Romain replicates applications and their resources completely and thereby does not rely on hardware extensions, such as ECC-protected memory. In my thesis I describe how to efficiently implement replication as a form of redundant multithreading in software. I develop mechanisms to manage replica resources and to make multi-threaded programs behave deterministically for replication. I furthermore present an approach to handle applications that use shared-memory channels with other programs. My evaluation shows that Romain provides 100% error detection and more than 99.6% error correction for single-bit flips in memory and general-purpose registers. At the same time, Romain's execution time overhead is below 14% for single-threaded applications running in triple-modular redundant mode. The last part of my thesis acknowledges that software-implemented fault tolerance methods often rely on the correct functioning of a certain set of hardware and software components, the Reliable Computing Base (RCB). I introduce the concept of the RCB and discuss what constitutes the RCB of the ASTEROID system and other fault tolerance mechanisms. Thereafter I show three case studies that evaluate approaches to protecting RCB components and thereby aim to achieve a software stack that is fully protected against hardware errors