A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.IMEC, Eindhoven, Netherland

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, 0.005/fs]

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, 0.005/fs]