37,016 research outputs found
A practical floating-gate Muller-C element using vMOS threshold gates
This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation
OverFeat: Integrated Recognition, Localization and Detection using Convolutional Networks
We present an integrated framework for using Convolutional Networks for
classification, localization and detection. We show how a multiscale and
sliding window approach can be efficiently implemented within a ConvNet. We
also introduce a novel deep learning approach to localization by learning to
predict object boundaries. Bounding boxes are then accumulated rather than
suppressed in order to increase detection confidence. We show that different
tasks can be learned simultaneously using a single shared network. This
integrated framework is the winner of the localization task of the ImageNet
Large Scale Visual Recognition Challenge 2013 (ILSVRC2013) and obtained very
competitive results for the detection and classifications tasks. In
post-competition work, we establish a new state of the art for the detection
task. Finally, we release a feature extractor from our best model called
OverFeat
Techniques for the Synthesis of Reversible Toffoli Networks
This paper presents novel techniques for the synthesis of reversible networks
of Toffoli gates, as well as improvements to previous methods. Gate count and
technology oriented cost metrics are used. Our synthesis techniques are
independent of the cost metrics. Two new iterative synthesis procedure
employing Reed-Muller spectra are introduced and shown to complement earlier
synthesis approaches. The template simplification suggested in earlier work is
enhanced through introduction of a faster and more efficient template
application algorithm, updated (shorter) classification of the templates, and
presentation of the new templates of sizes 7 and 9. A novel ``resynthesis''
approach is introduced wherein a sequence of gates is chosen from a network,
and the reversible specification it realizes is resynthesized as an independent
problem in hopes of reducing the network cost. Empirical results are presented
to show that the methods are effective both in terms of the realization of all
3x3 reversible functions and larger reversible benchmark specifications.Comment: 20 pages, 5 figure
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