This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation

Avedillo de Juan, María José

Huertas Sánchez, Gloria

Quintana Toledo, José María

Rodríguez Villegas, Esther

Rueda Rueda, Adoración

English

idUS. Depósito de Investigación Universidad de Sevilla

A PRACTICAL FLOATING-GATE MULLER-C ELEMENT USING νMOSTHRESHOLD GATESE. Rodríguez-Villegas, G. Huertas, M.J. Avedillo, J.M. Quintana, and A. RuedaInstituto de Microlectrónica de Sevilla (IMSE-CNM)Edif. CICA, Avda. Reina Mercedes s/n, 41012 Sevilla, SPAIN.Indexing Terms: Threshold logic design, Concurrence elements, Neuron-MOS transistorapplications.Abstract:This paper presents the rationale for νMOS-based realizations of digital circuits when logicdesign techniques based on threshold logic gates (TGs) are used. Some practical problems inthe νMOS implementation of threshold gates have been identified and solved. The feasibilityand versatility of the proposed technique as well as its potential as a low-cost design techniquefor CMOS technologies have been shown by experimental results from a multi-input MullerC-element. The proposed new realization exhibits better performance related to delay, area andpower consumption than the traditional logic implementation.I. IntroductionNeuron MOS (νMOS) transistor principle [1] has been identified as one of the most prom-ising ways to realize ultra large logic circuits [2-5], because the enhancement in the functionalcapability of an elemental transistor makes it very effective in reducing the complexity of thetotal circuit. The νMOS transistor has a buried floating polysilicon gate and a number of inputpolysilicon gates that couple capacitively to the floating gate [1-3]. The voltage of the floating2gate becomes a weighted sum of the voltages in the input gates, and hence, is this sum whichcontrols the current in the transistor channel.Logic design techniques for implementation of νMOS circuits have been carried out by Shibata[2,3], but their usefulness is limited because, in general, it leads to complex circuit configurationswhich require handling 2n logic states for an n-input logic function. This imposes stringent con-straints on process tolerances, not realizable by present technologies for even a relative small n.A different and more powerful approach for the logic design takes advantage of the fact thatthe functionality of νMOS circuits is closely related to that of a threshold logic gate (TG) [5,14]. The existence of logic design techniques which use TGs as building blocks [6, 7, 8] easesthe synthesis of complex functions. Threshold logic gates have n two-valued inputs x1, x2, …,xn and a single two-valued output, y. They are defined by n+1 real numbers: threshold T andweights w1, w2, …, wn, where weight wi is associated with variable xi. The input-output relationof a threshold gate is defined as y=1 iff and y=0 otherwise. Sum and product arethe conventional, rather than the logical, operations. The set of weights and threshold can bedenoted in a more compact vector notation way by .In this paper we report on a working νMOS-based logic circuit specifically devised to validatethe design approach using νMOS-based TGs. The paper is organized as follows. Section II de-scribes the implementation of TGs with νMOS transistors, first at a theoretical level and then, dis-cussing practical considerations. The design and experimental results for an 8 input Muller C-el-ement are given in Section III, and finally, some conclusions are discussed in Section IV.II. νMOS Implementation of Threshold GatesA) Theoretical backgroundThe most simple νMOS-based threshold gate (νMOS-TG) is the complementary inverterusing both p- and n-type νMOS devices. A schematic of this TG is shown in Fig. 1. It consistswixi T≥i 1=n∑w1 w2 … wn T;, , ,[ ]3in a floating gate, which is common to both the PMOS and the NMOS transistors, and a numberof input gates (Vx1, Vx2, ..., Vxn), corresponding to the threshold gate inputs plus an extra input(indicated by in the figure) for logic threshold adjustment as will be explained later. With-out using the extra control input, and assuming the charge in the floating gate is zero, the volt-age in the floating gate is given by , where is the couplingcapacitance between the i-th input and the floating gate, and is the total capacitance, in-cluding the parasitic capacitances at the floating gate , . As be-comes higher than the inverter threshold voltage, VTH, the output switches to logic 1.A CMOS TG has digital entries, i.e., , where is the power supply and. A relation between the expression for and that of the definition of the TG can beestablished as the weighted summation in the TG, , is implemented by the capacitive net-work in the νMOS device, . The weight for each input is proportional tothe ratio between the corresponding input capacitance and ( ). Thus,design involves mapping the logical inequalities and to the electricalrelations and through capaci-tance sizing and tuning of the threshold voltage of the inverter.When logical threshold T is not centred (i.e., T is far from ), the threshold volt-age of the inverter would have to be also non centred (near 0 or VDD). This can be achievedusing extra inputs. For example, let us assume a single control input with capacitance CControl.If Vc is applied to this control input, the new is:whereVcV F CiV xii 1=n∑   Ctot⁄= CiCtotCc Ctot Cii 1=n∑ Cc+= V FV xi xiV DD= VDDxi 0 1{ , }∈ V Fwixii 1=n∑CixiV DDi 1=n∑   Ctot⁄Ci Ctot wi CiV DD Ctot⁄=wixi T≥i 1=n∑ wixi T<i 1=n∑CixiV DDi 1=n∑   Ctot⁄ VTH> CixiV DDi 1=n∑   Ctot⁄ VTH<wii 1=n∑   2⁄V FV F CixiV DDi 1=n∑   Ctot⁄ CControlVc( ) Ctot⁄+=Ctot Cii 1=n∑ Cc CControl+ +=4From the point of view of the TG a comparison is performed betweenand . Thus, the effective threshold voltage of the inverter has beenmodified. In practical digital design analog voltages are avoided and so the role of the analogextra input Vc is realized by a set of digital inputs with the appropriate coupling capacitances.Clearly, practical design requires considering second order effects not included for simplicity inthe above expressions. The main issue for the circuit in Fig. 1 is related with the coupling effect pro-duced when switching on the power supply. Transistor capacitances Cfd (between floating gate anddrain) and Cfs (between floating gate and source) are responsible for these couplings which intro-duce additional terms in VF. Sizing of input capacitors and transistors should be performed on thebasis of reducing these extra terms, or also of adequately controlling the effective inverter thresholdvoltage. In addition, there could be parasitic charge in the floating gate after fabrication and it is ob-vious that the circuit operation is sensitive to it. For this effect, UV erasure is recommended.B) Practical design aspectsBeside the theoretical background for the realization of TGs with νMOS devices, practical de-sign and implementation of these gates require taking into account and solving the following issues.a) Signal regeneration. Clearly these TGs exhibit reduced noise margins as a consequenceof the electrical operation of the circuit. On the other hand, some input combinations can pro-duce output voltages different from VDD or ground. These two considerations are speciallycritical when logic networks are built up interconnecting νMOS-TGs. Thus the inverter I inFigure 1 should be seen as an inverting signal regeneration stage.b) Electrical simulation. During the design phase, electrical simulations for validation mustbe performed, and hence, good models for floating-gate MOSFETs should be used. Since man-CixiV DDi 1=n∑   Ctot⁄VTH CControlVc( ) Ctot⁄–5ufacters do not provide these models, techniques to simulate floating gate devices with standardMOS models must be devised. Other of the difficulties in simulating floating gate devices relieson the inability of the simulator to converge when floating nodes exist. An initial operating pointof the circuit must be introduced. Previous approaches for this problem are given in [9, 10]. Theyuse an additional network formed by resistors and VCVSs (Voltage Controlled Voltage Sourc-es) to establish the initial floating-gate voltage value. The main problem of these approaches isthat an operation point is previously determined to fix the value of the voltages at the VCVS con-trol terminals. Those values are then assumed constant for all the rest of the circuit operation.This last is not completely correct because of the nonlinear relationship between the floating-gate voltage and the voltages in the other device terminals (drain, source), depending on the tran-sistor operation region. The simple procedure we have devised [11] overcomes the above prob-lem. It is based on performing a transient analysis which starts with all the power supplies andcircuit inputs set to zero. Thus, initial condition for the floating-gate voltage provided to the sim-ulator is zero. Afterwards, in the same transient analysis, power and inputs are set to their values.The stationary state reached provides the correct initial operation which can be used for the restof simulations. In order to illustrate the accuracy of our method the circuit shown in Fig. 2(a)has been designed and fabricated. It consists of two cascaded inverters. The first one is imple-mented using νMOS devices and the second is a conventional logic CMOS inverter for signalregeneration. The circuit has two inputs Vin and Vc with equal coupling capacitances (C=70fF).It behaves like an inverter with input Vin and threshold voltage varying with Vc. Both invertersare equally sized. In Fig. 2(b), one of the simulations performed for obtaining the transfer char-acteristics for nodes Vout1 and Vout is shown to illustrate our simulation approach. Notice thatthe initial value of VF is provided by the simulator taking into account all the parasitic couplingeffects. Figure 3 compares the experimental measurements obtained after UV erasure with thesimulation results obtained following our technique and the approach in [9]. Input-output char-6acteristics for different values of Vc (0, 1, 2, 3, 4 and 5 volts) are shown. Agreement betweensimulation with our technique (Figure 3a) and experimental (Figure 3c) is observed. Howeverthe results obtained with the technique in [9] (Figure 3b) differ from the experimental ones sincethe simulated threshold voltages of the inverter appear shifted to the right. The feasibility of theproposed simulation technique to analog circuits has been also experimentally verified [11].III. Application Example: A Multi-Input Muller C-elementA Muller C-element (where the C stands for concurrence) is a circuit widely used in the de-sign of self-timing circuits to perform the function “and” of events (transitions 1→0 or 0→1).Its output is made equal to the value of input after all the input reach the same value; otherwise,the output remains the same. It has been proven [12] that an m-input Muller C-element can beimplemented using a single threshold gate with (m+1) inputs, and the simplest solution is ob-tained when the primary inputs have an associated weight of 1, the (m+1)-th input (the feedbackinput) is affected by a weight of (m-1), and the threshold of the TG is m, as shown in Figure 4a.The complexity of this logic element is high enough for serving as a good demonstrator ofthe feasibility of the proposed design approach based on νMOS-TG. On one hand, it shows thata complex functionality can be implemented by a single inverter. On the other, the existence ofa feedback loop with a high associated weight (m-1) allows testing the signal regeneration ca-pability that would guarantee the correct operation of threshold networks.Figure 4b depicts the νMOS realization we propose for the logic diagram shown in Figure4, when m= 8. This circuit has been designed and fabricated in an 0.8µm double poly CMOStechnology. Operation under process and ambient parameters has been validated through ex-tensive HSPICE simulations of the extracted circuit including Monte Carlo simulations andsimulations using different standard worst case device parameters. Figure 5 shows the respons-es obtained in the laboratory. Waveform at the bottom trace is the circuit output and the remain-7ing waveforms correspond to the circuit signal inputs. Notice that operation is correct. This cor-rect operation has been observed in the laboratory with the supply voltage down to 3V.For comparison purposes we have also designed and laid-out a conventional 8 input MullerC-element following the structure proposed in [13] which has been shown to be very efficient.Table I compares the area, time performance and power consumption of both Muller C-ele-ments.IV ConclusionsWe have exploited the relationship between the νMOS transistor principle and the thresholdgate concept. On its basis a new νMOS realization for multi-input Muller C-elements has beenproposed and its feasibility demonstrated with an eight input Muller C-element working in sili-con. Compared to a conventional gate-based implementation, the νMOS design is very efficient.It occupies half the area than its conventional counterpart, exhibits better time performance andconsumes significantly less power. In addition, an electrical simulation technique for floatinggate devices has been described and its accuracy has been proven experimentally.References1 T. Shibata, T. Ohmi, “A functional MOS transistor featuring gate level weighted sum andthreshold operations”, IEEE J. Solid-State Circ., vol. 39, pp. 1444-1445, 1992.2 -------, “Neuron MOS binary-logic integrated circuits- Part I: Design fundamentals andsoft-hardware-logic circuit implementations”, IEEE Trans. Electron Devices, vol. 40, pp.570-576, 19933 -------,“Neuron MOS binary-logic integrated circuits- Part II: Simplifying techniques ofCircuit Configuration and their Practical Applications”, IEEE Trans. Electron Devices,vol. 40, pp. 974-979, 1993.84 W. Weber, et al., “On the application of the Neuron MOS Transistor Principle for Mod-ern VLSI Design”, IEEE Tran. Electron Devices, vol. 43, No. 10, pp. 1700-1708, Octo-ber 1996.5 K.F. Goser, C. Pacha, A. Kanstein, and M.L. Rossmann, “Aspects of Systems and Cir-cuits for Nanoelectronics”, Proc. of the IEEE, Vol. 85, No. 4, pp. 558-573.6 S. Muroga, Threshold Logic & its Applications, New York: John Wiley & Sons, 1971.7 A. L. Oliveira and A. Sangiovanni-Vincentelli, LSAT- An Algorithm for the Synthesisof Two Level Threshold Gate Networks, Proc Int. Conf. on Computer Aided Design, pp.130-133, 1991.8 K. Siu and V.P. Roychowdhury, An Optimal-depth Threshold Circuit for Multiplicationand Related Problems, SIAM Journal of Discrete Mathematics, 7, (2): 284-292, 19949 J. Ramirez-Angulo, G. Gonzalez-Altamirano and S.C. Choi, “Modeling Multiple-InputFloating-Gate Transistors for Analog Signal Processing”, IEEE Int. Symp. on Circuitsand Systems, pp. 2020-2023, 1997.10 L. Yin, S.H.K. Embabi and E. Sánchez-Sinencio, “A Floating-Gate MOSFET D/A Con-verter”, IEEE International Symposium on Circuits and Systems, pp. 409-412, 1997.11 E. Rodriguez-Villegas “Working with FGMOS”, Internal Report, Instituto de Microelec-tronica de Sevilla, IMSE-CNM, 1998.12 J.M. Quintana, M.J. Avedillo, A. Rueda y S. Baena, “Practical Low-Cost CMOS realiza-tion of Complex Logic Functions”, Proc. of European Conf. on Circuit Theory and De-sign, ECCTD’95, pp. 51-54.13 T.-Y. Wuu and S.B.K. Vrudhula, “A Design of a Fast and Area Efficient Multi-InputMuller C-element”, IEEE Trans. on VLSI Systems, vol. 1, no. 2, pp. 215-219, June 1993.14 M.J. Avedillo, J.M. Quintana, and A. Rueda, “Threshold Logic”, Wiley Encyclopedia ofElectrical and Electronics Engineering, J.G. Webster, Ed., Vol. 22, pp. 178-190, 1999.9Captions to the Figures:Figure 1: vMOS threshold gate schematicFigure 2: a) Floating-gate CMOS inverter with threshold control;b) Transient simulation performed to obtain transfer characteristic of circuit inFigure 2a for Vc = 3VFigure 3: Simulation and experimental input-output characteristics for the circuit in Fig. 2a:a) Simulation results with our technique;b) Simulation results with the technique in [9];c) Experimental resultsFigure 4: a) Threshold-gate-based m-input Muller C-element realization;b)Electrical diagram of vMOS-based 8 input Muller C-elementFigure 5: Experimental waveforms of vMOS-based 8 input Muller C-elementCaptions to the Tables:Table I: Performance parameters for vMOS and conventional 8-input Muller C-elements10FIGURESFigure 1PMOSNMOSfVx1Vx2Vx3VxnVFVcIVDDVoutVinVcFigure 2aVout1VDD6.5/23/20 100n 200n0.01.02.03.04.05.0VDDVout1Vout VinVFGFigure 2bVctimeVoltages11areaworst casedelaypower consumption(@100MHz)νMOS 4927 µm2 1.8 ns 0.03 mwconventional 9942 µm2 3.2 ns 0.54 mwTable 1:SymbolWaveD0:A0:v(out)D0:A0:v(out1)Voltages (lin)0500m11.522.533.544.55Voltages (lin) (cont)0 500m 1 1.5 2 2.5 3 3.5 4 4.5 5* # file name: /mnt/cnm/esther/fgmos/sim/inversor/hspices/extracted/543210Voltages (lin)0 1 2 3 4 5Voltages (lin) (cont)VoutVout1SymbolWaveD2:A0:v(out)D2:A0:v(out1)Voltages (lin)0500m11.522.533.544.55Voltages (lin) (cont)0 500m 1 1.5 2 2.5 3 3.5 4 4.5 5* # file name: /mnt/cnm/esther/fgmos/sim/inversor/hspices/extracted/543210Voltages (lin)0 1 2 3 4 5Voltages (lin) (cont)Vo tVout1Figure 3aFigure 3b12Figure 3cVx1Vx8 Vout(b)C (115fF)7Cx1x2xmQFigure 4U: [1,1,...,1,m-1;m]TG(a)VDD4/23.5/2000001011Figure 513

A practical floating-gate Muller-C element using vMOS threshold gates

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A practical floating-gate Muller-C element using vMOS threshold gates

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idUS. Depósito de Investigación Universidad de Sevilla