2 research outputs found
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Ring amplification for switched capacitor circuits
A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification
Time interleaved counter analog to digital converters
The work explores extending time interleaving in A/D converters, by
applying a high-level of parallelism to one of the slowest and simplest types of
data-converters, the counter ADC. The motivation for the work is to realise
high-performance re-configurable A/D converters for use in multi-standard and
multi-PHY communication receivers with signal bandwidths in the 10s to 100s of
MHz. The counter ADC requires only a comparator, a ramp signal, and a
digital counter, where the comparator compares the sampled input against all
possible quantisation levels sequentially. This work explores arranging counter
ADCs in large time-interleaved arrays, building a Time Interleaved Counter
(TIC) ADC. The key to realising a TIC ADC is distributed sampling and a
global multi-phase ramp generator realised with a novel figure-of-8 rotating
resistor ring. Furthermore Counter ADCs allow for re-configurability between
effective sampling rate and resolution due to their sequential comparison of
reference levels in conversion. A prototype TIC ADC of 128-channels was
fabricated and measured in 0.13μm CMOS technology, where the same block can
be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter.
The ADC achieves a sub 400fJ/step FOM in all modes of
configuration