FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grant TEC2008-06787.Canet Subiela, MJ.; Valls Coquillat, J.; Almenar Terré, V.; Marín-Roig Ramón, J. (2012). FPGA implementation of an OFDM-based WLAN receiver. Microprocessors and Microsystems. 36(3):232-244. https://doi.org/10.1016/j.micpro.2011.11.004S23224436

Design and Implementation of an OFDM WLAN Synchronizer

With the advent of OFDM for WLAN communications, as exemplified by IEEE 802.11a, it has become imperative to have efficient and reliable synchronization algorithms for OFDM WLAN receivers. The main challenges with synchronization deal with the delay spread and frequency offset introduced by the wireless channel. In this work, rigorous research is done into OFDM WLAN synchronization algorithms, and a thorough synchronizer implementation is presented. This synchronizer performs packet detection, frequency offset estimation, and time offset estimation. Competing timing offset estimation algorithms are compared under a variety of channel conditions, with varying delay spreads, frequency offsets, and channel SNR. The metrics used to select between competing algorithms are statistical variance, and incremental hardware complexity. The timing offset estimation algorithms chosen are a dropoff detection algorithm for coarse timing offset estimation, and a quantized cross-correlator with a maximum detector for fine timing offset estimation

Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles

In this paper, a new time synchronization algorithm for OFDM systems with repetitive preamble is proposed. This algorithm makes use of coarse and fine time estimation; the fine time estimation is performed using a cross-correlation similar to previous proposals in the literature, whereas the coarse time estimation is made using a new metric and an iterative search of the last sample of the repetitive preamble. A complete analysis of the new metric is included, as well as a wide performance comparison, for multipath channel and carrier frequency offset, with the main time synchronization algorithms found in the literature. Finally, the complexity of the VLSI implementation of this proposal is discussed. © 2011 Springer Science+Business Media, LLC.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grants TEC2006-14204-C02-01 and TEC2008-06787.Canet Subiela, MJ.; Almenar Terre, V.; Flores Asenjo, SJ.; Valls Coquillat, J. (2012). Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles. Journal of Signal Processing Systems. 68(3):287-301. doi:10.1007/s11265-011-0618-6S287301683IEEE 802.11a standard (1999). Wireless LAN medium access control (MAC) and physical layer (PHY) specifications: high-speed physical layer in the 5 GHz band.IEEE 802.11 g standard (2003). Wireless LAN specifications: Further higher data rate extension in the 2.4 GHz band.IEEE 802.16-2004 (2004). Standard for local and metropolitan area networks, part 16: Air interface for fixed broadband wireless access systems.Lee, D., & Cheun, K. (2002). Coarse symbol synchronization algorithms for OFDM systems in multipath channels. IEEE Communications Letters, 6(10), 446–448.Park, B., Cheon, H., Ko, E., Kang, C., & Hong, D. (2004). A blind OFDM synchronization algorithm based on cyclic correlation. IEEE Signal Processing Letters, 11(2), 83–85.Beek, J. J., Sandell, M., & Börjesson, P. O. (1997). ML estimation of time and frequency offset in OFDM system. IEEE Transactions on Signal Processing, 45(7), 1800–1805.Ma, S., Pan, X., Yang, G., & Ng, T. (2009). Blind symbol synchronization based on cyclic prefix for OFDM systems. IEEE Transactions on Vehicular Technology, 58(4), 1746–1751.Schmidl, T., & Cox, D. (1997). Robust frequency and timing synchronization for OFDM. IEEE Transactions on Communications, 45(12), 1613–1621.Coulson, A. J. (2001). Maximum likelihood synchronization for OFDM using a pilot symbol: Algorithms. IEEE Journal on Selected Areas in Communications, 19(12), 2495–2503.Tufvesson, F., Edfors, O., & Faulker, M. (1999). Time and frequency synchronization for OFDM using PN-sequence preambles. Proceedings of the Vehicular Technology Conference (VTC), 4, 2203–2207.Shi, K., & Serpedin, E. (2004). Coarse frame and carrier synchronization of OFDM systems: a new metric and comparison. IEEE Transactions on Wireless Communications, 3(4), 1271–1284.Minn, H., Zeng, M., & Bhargava, V. K. (2000). On timing offset estimation for OFDM Systems. IEEE Communications Letters, 4, 242–244.Minn, H., Bhargava, V. K., & Letaief, K. B. (2003). A robust timing and frequency synchronization for OFDM systems. IEEE Transactions on Wireless Communications, 2(4), 822–839.Minn, H., Bhargava, V. K., & Letaief, K. B. (2006). A combined timing and frequency synchronization and channel estimation for OFDM. IEEE Transactions on Communications, 54(3), 416–422.Park, B., Cheon, H., Ko, E., Kang, C., & Hong, D. (2003). A novel timing estimation method for OFDM systems. IEEE Communications Letters, 7(5), 239–241.Chang, S., & Kelley, B. (2003). Time synchronization for OFDM-based WLAN systems. Electronics Letters, 39(13), 1024–1026.Wu, Y., Yip, K., Ng, T., & Serpedin, E. (2005). Maximum-likelihood symbol synchronization for IEEE 802.11a WLANs in unknown frequency-selective fading channels. IEEE Transactions on Wireless Communications, 4(6), 2751–2763.Larsson, E. G., Liu, G., Li, J., & Giannakis, G. B. (2001). Joint symbol timing and channel estimation for OFDM based WLANs. IEEE Communications Letters, 5(8), 325–327.Troya, A., Maharatna, K., Krstic, M., Grass, E., Jagdhold, U., & Kraemer, R. (2007). Efficient inner receiver design for OFDM-based WLAN systems: algorithm and architecture. IEEE Transactions on Wireless Communications, 6(4), 1374–1385.Yang, J., & Cheun, K. (2006). Improved symbol timing synchronization in IEEE 802.11a/g wireless LAN systems in multipath channels. International Conference on Consumer Electronics. doi: 10.1109/ICCE.2006.1598425 .Manusani, S. K., Hshetrimayum, R. S., & Bhattacharjee, R. (2006). Robust time and frequency synchronization in OFDM based 802.11a WLAN systems. Annual India Conference. doi: 10.1109/INDCON.2006.302775 .Zhou, L., & Saito, M. (2004). A new symbol timing synchronization for OFDM based WLANs under multipath fading channels. 15th IEEE International Symposium on Personal, Indoor and Mobile Radio Communications. doi: 10.1109/PIMRC.2004.1373890 .Kim, T., & Park, S.-C. (2007). A new symbol timing and frequency synchronization design for OFDM-based WLAN systems. 9th Conference on Advanced Communication Technology. doi: 10.1109/ICACT.2007.358691 .Baek, J. H., Kim, S. D., & Sunwoo, M. H. (2008). SPOCS: Application specific signal processor for OFDM communication systems. Journal of Signal Processing Systems, 53(3), 383–397.Van Kempen, G., & van Vliet, L. (2000). Mean and variance of ratio estimators used in fluorescence ratio imaging. Cytometry, 39(4), 300–305.J. Melbo, J., & Schramm, P. (1998). Channel models for HIPERLAN/2 in different indoor scenarios. 3ERI085B, HIPERLAN/2 ETSI/BRAN contribution.Abramowitz, M., & Stegun, I. A. (1972). Handbook of mathematical functions. Dover.López-Martínez, F. J., del Castillo-Sánchez, E., Entrambasaguas, J. T., & Martos-Naya, E. (2010). Iterative-gradient based complex divider FPGA core with dynamic configurability of accuracy and throughput. Journal of Signal Processing Systems. doi: 10.1007/s11265-010-0464-y .Angarita, F., Canet, M. J., Sansaloni, T., Perez-Pascual, A., & Valls, J. (2008). Efficient mapping of CORDIC Algorithm for OFDM-based WLAN. Journal of Signal Processing Systems, 52(2), 181–191

Design and implementation of a downlink MC-CDMA receiver

Cette thèse présente une étude d'un système complet de transmission en liaison descendante utilisant la technologie multi-porteuse avec l'accès multiple par division de code (Multi-Carrier Code Division Multiple Access, MC-CDMA). L'étude inclut la synchronisation et l'estimation du canal pour un système MC-CDMA en liaison descendante ainsi que l'implémentation sur puce FPGA d'un récepteur MC-CDMA en liaison descendante en bande de base. Le MC-CDMA est une combinaison de la technique de multiplexage par fréquence orthogonale (Orthogonal Frequency Division Multiplexing, OFDM) et de l'accès multiple par répartition de code (CDMA), et ce dans le but d'intégrer les deux technologies. Le système MC-CDMA est conçu pour fonctionner à l'intérieur de la contrainte d'une bande de fréquence de 5 MHz pour les modèles de canaux intérieur/extérieur pédestre et véhiculaire tel que décrit par le "Third Genaration Partnership Project" (3GPP). La composante OFDM du système MC-CDMA a été simulée en utilisant le logiciel MATLAB dans le but d'obtenir des paramètres de base. Des codes orthogonaux à facteur d'étalement variable (OVSF) de longueur 8 ont été choisis comme codes d'étalement pour notre système MC-CDMA. Ceci permet de supporter des taux de transmission maximum jusquà 20.6 Mbps et 22.875 Mbps (données non codées, pleine charge de 8 utilisateurs) pour les canaux intérieur/extérieur pédestre et véhiculaire, respectivement. Une étude analytique des expressions de taux d'erreur binaire pour le MC-CDMA dans un canal multivoies de Rayleigh a été réalisée dans le but d'évaluer rapidement et de façon précise les performances. Des techniques d'estimation de canal basées sur les décisions antérieures ont été étudiées afin d'améliorer encore plus les performances de taux d'erreur binaire du système MC-CDMA en liaison descendante. L'estimateur de canal basé sur les décisions antérieures et utilisant le critère de l'erreur quadratique minimale linéaire avec une matrice' de corrélation du canal de taille 64 x 64 a été choisi comme étant un bon compromis entre la performance et la complexité pour une implementation sur puce FPGA. Une nouvelle séquence d'apprentissage a été conçue pour le récepteur dans la configuration intérieur/extérieur pédestre dans le but d'estimer de façon grossière le temps de synchronisation et le décalage fréquentiel fractionnaire de la porteuse dans le domaine du temps. Les estimations fines du temps de synchronisation et du décalage fréquentiel de la porteuse ont été effectués dans le domaine des fréquences à l'aide de sous-porteuses pilotes. Un récepteur en liaison descendante MC-CDMA complet pour le canal intérieur /extérieur pédestre avec les synchronisations en temps et en fréquence en boucle fermée a été simulé avant de procéder à l'implémentation matérielle. Le récepteur en liaison descendante en bande de base pour le canal intérieur/extérieur pédestre a été implémenté sur un système de développement fabriqué par la compagnie Nallatech et utilisant le circuit XtremeDSP de Xilinx. Un transmetteur compatible avec le système de réception a également été réalisé. Des tests fonctionnels du récepteur ont été effectués dans un environnement sans fil statique de laboratoire. Un environnement de test plus dynamique, incluant la mobilité du transmetteur, du récepteur ou des éléments dispersifs, aurait été souhaitable, mais n'a pu être réalisé étant donné les difficultés logistiques inhérentes. Les taux d'erreur binaire mesurés avec différents nombres d'usagers actifs et différentes modulations sont proches des simulations sur ordinateurs pour un canal avec bruit blanc gaussien additif

Reconfigurable Antenna Systems: Platform implementation and low-power matters

Antennas are a necessary and often critical component of all wireless systems, of which they share the ever-increasing complexity and the challenges of present and emerging trends. 5G, massive low-orbit satellite architectures (e.g. OneWeb), industry 4.0, Internet of Things (IoT), satcom on-the-move, Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles, all call for highly flexible systems, and antenna reconfigurability is an enabling part of these advances. The terminal segment is particularly crucial in this sense, encompassing both very compact antennas or low-profile antennas, all with various adaptability/reconfigurability requirements. This thesis work has dealt with hardware implementation issues of Radio Frequency (RF) antenna reconfigurability, and in particular with low-power General Purpose Platforms (GPP); the work has encompassed Software Defined Radio (SDR) implementation, as well as embedded low-power platforms (in particular on STM32 Nucleo family of micro-controller). The hardware-software platform work has been complemented with design and fabrication of reconfigurable antennas in standard technology, and the resulting systems tested. The selected antenna technology was antenna array with continuously steerable beam, controlled by voltage-driven phase shifting circuits. Applications included notably Wireless Sensor Network (WSN) deployed in the Italian scientific mission in Antarctica, in a traffic-monitoring case study (EU H2020 project), and into an innovative Global Navigation Satellite Systems (GNSS) antenna concept (patent application submitted). The SDR implementation focused on a low-cost and low-power Software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. In a second embodiment, the flexibility of the SDR paradigm has been traded off to avoid the power consumption associated to the relevant operating system. Application field of reconfigurable antenna is, however, not limited to a better management of the energy consumption. The analysis has also been extended to satellites positioning application. A novel beamforming method has presented demonstrating improvements in the quality of signals received from satellites. Regarding those who deal with positioning algorithms, this advancement help improving precision on the estimated position

Multi-carrier transmission techniques toward flexible and efficient wireless communication systems

制度:新 ; 文部省報告番号:甲2562号 ; 学位の種類:博士(国際情報通信学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新470

Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases

[EN] The first generation of Terrestrial Digital Television(DTV) has been in service for over a decade. In 2013, several countries have already completed the transition from Analog to Digital TV Broadcasting, most of which in Europe. In South America, after several studies and trials, Brazil adopted the Japanese standard with some innovations. Japan and Brazil started Digital Terrestrial Television Broadcasting (DTTB) services in December 2003 and December 2007 respectively, using Integrated Services Digital Broadcasting - Terrestrial (ISDB-T), also known as ARIB STD-B31. In June 2005 the Committee for the Information Technology Area (CATI) of Brazilian Ministry of Science and Technology and Innovation MCTI approved the incorporation of the IC-Brazil Program, in the National Program for Microelectronics (PNM) . The main goals of IC-Brazil are the formal qualification of IC designers, support to the creation of semiconductors companies focused on projects of ICs within Brazil, and the attraction of semiconductors companies focused on the design and development of ICs in Brazil. The work presented in this thesis originated from the unique momentum created by the combination of the birth of Digital Television in Brazil and the creation of the IC-Brazil Program by the Brazilian government. Without this combination it would not have been possible to make these kind of projects in Brazil. These projects have been a long and costly journey, albeit scientifically and technologically worthy, towards a Brazilian DTV state-of-the-art low complexity Integrated Circuit, with good economy scale perspectives, due to the fact that at the beginning of this project ISDB-T standard was not adopted by several countries like DVB-T. During the development of the ISDB-T receiver proposed in this thesis, it was realized that due to the continental dimensions of Brazil, the DTTB would not be enough to cover the entire country with open DTV signal, specially for the case of remote localizations far from the high urban density regions. Then, Eldorado Research Institute and Idea! Electronic Systems, foresaw that, in a near future, there would be an open distribution system for high definition DTV over satellite, in Brazil. Based on that, it was decided by Eldorado Research Institute, that would be necessary to create a new ASIC for broadcast satellite reception. At that time DVB-S2 standard was the strongest candidate for that, and this assumption still stands nowadays. Therefore, it was decided to apply to a new round of resources funding from the MCTI - that was granted - in order to start the new project. This thesis discusses in details the Architecture and Algorithms proposed for the implementation of a low complexity Intermediate Frequency(IF) ISDB-T Receiver on Application Specific Integrated Circuit (ASIC) CMOS. The Architecture proposed here is highly based on the COordinate Rotation Digital Computer (CORDIC) Algorithm, that is a simple and efficient algorithm suitable for VLSI implementations. The receiver copes with the impairments inherent to wireless channels transmission and the receiver crystals. The thesis also discusses the Methodology adopted and presents the implementation results. The receiver performance is presented and compared to those obtained by means of simulations. Furthermore, the thesis also presents the Architecture and Algorithms for a DVB-S2 receiver targeting its ASIC implementation. However, unlike the ISDB-T receiver, only preliminary ASIC implementation results are introduced. This was mainly done in order to have an early estimation of die area to prove that the project in ASIC is economically viable, as well as to verify possible bugs in early stage. As in the case of ISDB-T receiver, this receiver is highly based on CORDIC algorithm and it was prototyped in FPGA. The Methodology used for the second receiver is derived from that used for the ISDB-T receiver, with minor additions given the project characteristics.[ES] La primera generación de Televisión Digital Terrestre(DTV) ha estado en servicio por más de una década. En 2013, varios países completaron la transición de transmisión analógica a televisión digital, la mayoría de ellas en Europa. En América del Sur, después de varios estudios y ensayos, Brasil adoptó el estándar japonés con algunas innovaciones. Japón y Brasil comenzaron a prestar el servicio de Difusión de Televisión Digital Terrestre (DTTB) en diciembre de 2003 y diciembre de 2007 respectivamente, utilizando Radiodifusión Digital de Servicios Integrados Terrestres (ISDB-T), también conocida como ARIB STD-B31. En junio de 2005, el Comité del Área de Tecnología de la Información (CATI) del Ministerio de Ciencia, Tecnología e Innovación de Brasil - MCTI aprobó la incorporación del Programa CI-Brasil, en el Programa Nacional de Microelectrónica (PNM). Los principales objetivos de la CI-Brasil son la formación de diseñadores de CIs, apoyar la creación de empresas de semiconductores enfocadas en proyectos de circuitos integrados dentro de Brasil, y la atracción de empresas de semiconductores interesadas en el diseño y desarrollo de circuitos integrados. El trabajo presentado en esta tesis se originó en el impulso único creado por la combinación del nacimiento de la televisión digital en Brasil y la creación del Programa de CI-Brasil por el gobierno brasileño. Sin esta combinación no hubiera sido posible realizar este tipo de proyectos en Brasil. Estos proyectos han sido un trayecto largo y costoso, aunque meritorio desde el punto de vista científico y tecnológico, hacia un Circuito Integrado brasileño de punta y de baja complejidad para DTV, con buenas perspectivas de economía de escala debido al hecho que al inicio de este proyecto, el estándar ISDB-T no fue adoptado por varios países como DVB-T. Durante el desarrollo del receptor ISDB-T propuesto en esta tesis, se observó que debido a las dimensiones continentales de Brasil, la DTTB no sería suficiente para cubrir todo el país con la señal de televisión digital abierta, especialmente para el caso de localizaciones remotas, apartadas de las regiones de alta densidad urbana. En ese momento, el Instituto de Investigación Eldorado e Idea! Sistemas Electrónicos, previeron que en un futuro cercano habría un sistema de distribución abierto para DTV de alta definición por satélite en Brasil. Con base en eso, el Instituto de Investigación Eldorado decidió que sería necesario crear un nuevo ASIC para la recepción de radiodifusión por satélite, basada el estándar DVB-S2. En esta tesis se analiza en detalle la Arquitectura y algoritmos propuestos para la implementación de un receptor ISDB-T de baja complejidad y frecuencia intermedia (IF) en un Circuito Integrado de Aplicación Específica (ASIC) CMOS. La arquitectura aquí propuesta se basa fuertemente en el algoritmo Computadora Digital para Rotación de Coordenadas (CORDIC), el cual es un algoritmo simple, eficiente y adecuado para implementaciones VLSI. El receptor hace frente a las deficiencias inherentes a las transmisiones por canales inalámbricos y los cristales del receptor. La tesis también analiza la metodología adoptada y presenta los resultados de la implementación. Por otro lado, la tesis también presenta la arquitectura y los algoritmos para un receptor DVB-S2 dirigido a la implementación en ASIC. Sin embargo, a diferencia del receptor ISDB-T, se introducen sólo los resultados preliminares de implementación en ASIC. Esto se hizo principalmente con el fin de tener una estimación temprana del área del die para demostrar que el proyecto en ASIC es económicamente viable, así como para verificar posibles errores en etapa temprana. Como en el caso de receptor ISDB-T, este receptor se basa fuertemente en el algoritmo CORDIC y fue un prototipado en FPGA. La metodología utilizada para el segundo receptor se deriva de la utilizada para el re[CA] La primera generació de Televisió Digital Terrestre (TDT) ha estat en servici durant més d'una dècada. En 2013, diversos països ja van completar la transició de la radiodifusió de televisió analògica a la digital, i la majoria van ser a Europa. A Amèrica del Sud, després de diversos estudis i assajos, Brasil va adoptar l'estàndard japonés amb algunes innovacions. Japó i Brasil van començar els servicis de Radiodifusió de Televisió Terrestre Digital (DTTB) al desembre de 2003 i al desembre de 2007, respectivament, utilitzant la Radiodifusió Digital amb Servicis Integrats de (ISDB-T), coneguda com a ARIB STD-B31. Al juny de 2005, el Comité de l'Àrea de Tecnologia de la Informació (CATI) del Ministeri de Ciència i Tecnologia i Innovació del Brasil (MCTI) va aprovar la incorporació del programa CI Brasil al Programa Nacional de Microelectrònica (PNM). Els principals objectius de CI Brasil són la qualificació formal dels dissenyadors de circuits integrats, el suport a la creació d'empreses de semiconductors centrades en projectes de circuits integrats dins del Brasil i l'atracció d'empreses de semiconductors centrades en el disseny i desenvolupament de circuits integrats. El treball presentat en esta tesi es va originar en l'impuls únic creat per la combinació del naixement de la televisió digital al Brasil i la creació del programa Brasil CI pel govern brasiler. Sense esta combinació no hauria estat possible realitzar este tipus de projectes a Brasil. Estos projectes han suposat un viatge llarg i costós, tot i que digne científicament i tecnològica, cap a un circuit integrat punter de baixa complexitat per a la TDT brasilera, amb bones perspectives d'economia d'escala perquè a l'inici d'este projecte l'estàndard ISDB-T no va ser adoptat per diversos països, com el DVB-T. Durant el desenvolupament del receptor de ISDB-T proposat en esta tesi, va resultar que, a causa de les dimensions continentals de Brasil, la DTTB no seria suficient per cobrir tot el país amb el senyal de TDT oberta, especialment pel que fa a les localitzacions remotes allunyades de les regions d'alta densitat urbana.. En este moment, l'Institut de Recerca Eldorado i Idea! Sistemes Electrònics van preveure que, en un futur pròxim, no hi hauria a Brasil un sistema de distribució oberta de TDT d'alta definició a través de satèl¿lit. D'acord amb això, l'Institut de Recerca Eldorado va decidir que seria necessari crear un nou ASIC per a la recepció de radiodifusió per satèl¿lit. basat en l'estàndard DVB-S2. En esta tesi s'analitza en detall l'arquitectura i els algorismes proposats per l'execució d'un receptor ISDB-T de Freqüència Intermèdia (FI) de baixa complexitat sobre CMOS de Circuit Integrat d'Aplicacions Específiques (ASIC). L'arquitectura ací proposada es basa molt en l'algorisme de l'Ordinador Digital de Rotació de Coordenades (CORDIC), que és un algorisme simple i eficient adequat per implementacions VLSI. El receptor fa front a les deficiències inherents a la transmissió de canals sense fil i els cristalls del receptor. Esta tesi també analitza la metodologia adoptada i presenta els resultats de l'execució. Es presenta el rendiment del receptor i es compara amb els obtinguts per mitjà de simulacions. D'altra banda, esta tesi també presenta l'arquitectura i els algorismes d'un receptor de DVB-S2 de cara a la seua implementació en ASIC. No obstant això, a diferència del receptor ISDB-T, només s'introdueixen resultats preliminars d'implementació en ASIC. Això es va fer principalment amb la finalitat de tenir una estimació primerenca de la zona de dau per demostrar que el projecte en ASIC és econòmicament viable, així com per verificar possibles errors en l'etapa primerenca. Com en el cas del receptor ISDB-T, este receptor es basa molt en l'algorisme CORDIC i va ser un prototip de FPGA. La metodologia utilitzada per al segon receptor es deriva de la utilitzada per al receptor IRodrigues De Lima, E. (2016). Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/61967TESI

On Efficient Signal Processing Algorithms for Signal Detection and PAPR Reduction in OFDM Systems

The driving force of the study is susceptibility of LS algorithm to noise. As LS algorithm is simple to implement, hence it’s performance improvement can contribute a lot to the wireless technology that are especially deals with high computation. Cascading of AdaBoost algorithm with LS greatly influences the OFDM system performance. Performance of Adaptive Boosting based symbol recovery was investigated on the performance of LS, MMSE, BLUE were also compared with the performance of AdaBoost algorithm and MMSE has been found the higher computational complexity. Furthermore, MMSE also requires apriori channel statistics and computational complexity O(5N3) of the MMSE increases exponentially as the number of carrier increases. For the Adaboost case the computational complexity calculation is little different.Therefore, in the training stage of the AdaBoost algorithm, the computational complexity is only O(nT M) Furthermore, as it is a classification algorithm so in the receiver side we will require a separate de-mapper (or decoder) to get the desired data bits, i.e., a. SAS aided DCT based PAPR reduction 1326 and b. SAS aided DCT based PAPR reduction. A successive addition subtraction preprocessed DCT based PAPR reduction technique was proposed. Here, the performance of proposed method was compared with other preexisting techniques like SLM and PTS and the performance of the proposed method was seen to outperform specially in low PAPR region. In the proposed PAPR reduction method, the receiver is aware of the transmitted signal processing, this enables a reverse operation at the receiver to extract the transmit data. Hence the requirement of sending extra information through extra subcarrier is eliminated. The proposed method is also seen to be spectrally efficient. In the case of PTS and SLM it is inevitable to send the side information to retrieve the transmit signal. Hence, these two methods are spectrally inefficient. Successive addition subtraction based PAPR reduction method was also applied to MIMO systems. The performance of the SAS based PAPR reduction method also showed better performance as compared to other technique. An extensive simulation of MIMO OFDM PAPR reduction was carried out by varying the number of subcarriers and number of transmitter antennas. A detailed computational complexity analysis was also carried out. BATE aided SDMA multi user detection. A detailed study of SDMA system was carried out with it’s mathematical analysis.Many linear and non linear detectors like ML, MMSE, PIC, SIC have been proposed in literature for multiuser detection of SDMA system. However, except MMSE every receivers other are computational extensive. So as to enhance the performance of the MMSE MUD a meta heuristic Bat algorithm was incorporated in cascade with MMSE