2,269 research outputs found
A review of advances in pixel detectors for experiments with high rate and radiation
The Large Hadron Collider (LHC) experiments ATLAS and CMS have established
hybrid pixel detectors as the instrument of choice for particle tracking and
vertexing in high rate and radiation environments, as they operate close to the
LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for
which the tracking detectors will be completely replaced, new generations of
pixel detectors are being devised. They have to address enormous challenges in
terms of data throughput and radiation levels, ionizing and non-ionizing, that
harm the sensing and readout parts of pixel detectors alike. Advances in
microelectronics and microprocessing technologies now enable large scale
detector designs with unprecedented performance in measurement precision (space
and time), radiation hard sensors and readout chips, hybridization techniques,
lightweight supports, and fully monolithic approaches to meet these challenges.
This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog.
Phy
Delay and Power Reduction in Deep Submicron Buses
As technology scales down, coupling between nodes of the circuits increases and becomes an important factor in interconnection analysis. In many cases like the deep submicron technology (DSM), the coupling between lines (inter-wire capacitance) is strong and the energy consumption caused by parasitic capacitance is non-negligible. In this work, we employ the differential low-weight encoding [1] to reduce energy and delay (transmission cost) on DSM buses. We propose an enumeration method that reduces the encoder table-size from O(2n) words to O(n) words, for an n-bit DSM bus, and so reduces the memory complexity significantly and facilitates energy and delay reduction due to addressing and fetching data from large lookup tables. We modify the energy and delay equations for DSM buses and develop new representations in terms of number of the same and opposite direction transitions on the bus and use them in our interconnect analysis. We also use these equations to develop formulas for computing the mean transmission cost per bit on DSM buses for both differential low-weight encoding and uncoded schemes. Using the interconnect analysis, we compute a help codeword (from the set of unselected codewords) on the fly and assign to each selected codeword. This low complexity step consists of simple operations and enables us to gain more cost reduction without increasing the table size or number of the bus lines. The simulation results for 16-bit, 32-bit and 64-bit buses at maximum rate (only one extra line added) show that the proposed encoding scheme achieves more than 10% cost reduction, and performs more than 2.5% better than to the original differential low-weight scheme, in the worst case
Low-Frequency Noise Phenomena in Switched MOSFETs
In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, the authors review the limitations of current compact noise models which do not model such single-electron effects. The authors present measurement results that illustrate typical LF noise behavior in small-area MOSFETs, and a model based on Shockley-Read-Hall statistics to explain the behavior. Finally, the authors treat practical examples that illustrate the relevance of these effects to analog circuit design. To the analog circuit designer, awareness of these single-electron noise phenomena is crucial if optimal circuits are to be designed, especially since the effects can aid in low-noise circuit design if used properly, while they may be detrimental to performance if inadvertently applie
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