낸드 플래시 메모리 신뢰도 향상을 위한 신호 처리 방법 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 성원용.The capacity of NAND flash memory has been continuously increased by aggressive technology scaling and multi-level cell (MLC) data coding. However, it becomes more challenging to maintain the current growth rate of the memory density mainly because of degraded signal quality of sub-20 nm NAND flash memory. This dissertation develops signal processing techniques to improve the signal reliability of MLC NAND flash memory. In the first part of this dissertation, we develop two threshold voltage distribution estimation algorithms to compensate the effect of program-erase (PE) cycling and charge loss in MLC NAND flash memory. The sensing directed estimation (SDE) utilizes the output of multi-level memory sensing to estimate the means and the variances of the threshold voltage distribution that is modeled as a Gaussian mixture. In order to reduce memory sensing overheads for the SDE algorithm, we develop a decision directed estimation (DDE) that uses error corrected bit patterns for more frequent updates of the model parameters. We also present a combined estimation scheme that employs both the SDE and the DDE approaches to minimize the number of memory sensing operations while maintaining the estimation accuracy. The effectiveness of the SDE and the DDE algorithms is evaluated by using both simulated and real NAND flash memory, and it is demonstrated that the proposed algorithms can estimate the statistical information of threshold voltage distribution accurately. The cell-to-cell interference (CCI) is one of the major sources of bit errors in sub-20 nm NAND flash memory and becomes more severe as the size of memory cell decreases. In the second part of this dissertation, we develop a CCI cancellation algorithm that is similar to interference cancellers employed in conventional communication systems. We first provide the experimental characterization of the CCI by measuring the coupling coefficients from actual NAND flash memory with a 26 nm process technology. Then, we present a CCI cancellation algorithm that consists of the coupling coefficient estimation and the CCI removal steps. To reduce the number of memory sensing operations, the optimal quantization schemes for the proposed CCI canceller are also studied. This dissertation also develops soft-information computation schemes in order to apply soft-decision error correction to NAND flash memory. The probability density function (PDF) of the CCI removed signal is quite different from that of the original threshold voltage, which can be modeled as a Gaussian mixture. Thus, computing soft-information, such as LLR (log likelihood ratio), with the CCI removed signal is not straightforward. We propose two soft-information computation schemes that combine CCI cancellation and soft-decision error correction. In the first approach, we derive a mathematical formulation for the PDF of the CCI removed signal and directly compute the LLR values by using it. In the second approach, CCI cancellation and soft-information computation are jointly conducted. Based on the intensive simulations, it is demonstrated that the reliability of NAND flash memory is significantly improved by applying the proposed signal processing algorithms as well as soft-decision error correction.1 Introduction 14 2 NAND Flash Memory Basics 19 2.1 Basics of NAND Flash Memory 19 2.1.1 NAND Flash Memory Structure 19 2.1.2 Multi-Page Programming 20 2.1.3 Cell-to-Cell Interference 22 2.1.4 Data Retention 23 2.2 Threshold Voltage Distribution of NAND Flash Memory and Signal Modeling 25 2.2.1 Threshold Voltage Distribution and Gaussian Approximation 25 2.2.2 Modeling of Threshold Voltage Signal 27 3 Threshold Voltage Distribution Estimation 31 3.1 Introduction 31 3.2 Sensing Directed Estimation of Threshold Voltage Distribution 33 3.2.1 Cost Function 34 3.2.2 Gradient Descent Method based Parameter Search 36 3.2.3 Levenberg-Marquardt Method based Parameter Search 38 3.2.4 Experimental Results 41 3.3 Decision Directed Estimation of Threshold Voltage Distribution 50 3.3.1 Basic Idea 51 3.3.2 Applying to Two-Bit MLC NAND Flash Memory 54 3.3.3 Combined Threshold Voltage Distribution Estimation 57 3.3.4 Error Analysis 58 3.3.5 Experimental Results 64 3.4 Concluding Remarks 70 4 Cell-to-Cell Interference Cancellation 71 4.1 Introduction 71 4.2 Direct Measurement of Coupling Coefficients 73 4.2.1 Measurement Procedure 74 4.2.2 Experimental Results 77 4.3 Least Squares Method based Coupling Coefficient Estimation 83 4.4 Multi-Level Memory Sensing Schemes for CCI Cancellation 87 4.5 Experimental Results 91 4.5.1 CCI Cancellation with Simulated NAND Flash Memory 91 4.5.2 CCI Cancellation with Real NAND Flash Memory 96 4.6 Concluding Remarks 97 5 Soft-Decision Error Correction in NAND Flash Memory 99 5.1 Introduction 99 5.2 Soft-Decision Error Correction without CCI Cancellation 101 5.3 Soft-Decision Error Correction with CCI Cancellation 104 5.3.1 Soft-Information Computation using PDF of CCI Removed Signal 104 5.3.2 Joint CCI Cancellation and Soft-Information Computation 110 5.3.3 Experimental Results 115 5.4 Concluding Remarks 118 6 Conclusion 120Docto

Stash in a Flash

Encryption is a useful tool to protect data confidentiality. Yet it is still challenging to hide the very presence of encrypted, secret data from a powerful adversary. This paper presents a new technique to hide data in flash by manipulating the voltage level of pseudo-randomlyselected flash cells to encode two bits (rather than one) in the cell. In this model, we have one “public” bit interpreted using an SLC-style encoding, and extract a private bit using an MLC-style encoding. The locations of cells that encode hidden data is based on a secret key known only to the hiding user. Intuitively, this technique requires that the voltage level in a cell encoding data must be (1) not statistically distinguishable from a cell only storing public data, and (2) the user must be able to reliably read the hidden data from this cell. Our key insight is that there is a wide enough variation in the range of voltage levels in a typical flash device to obscure the presence of fine-grained changes to a small fraction of the cells, and that the variation is wide enough to support reliably re-reading hidden data. We demonstrate that our hidden data and underlying voltage manipulations go undetected by support vector machine based supervised learning which performs similarly to a random guess. The error rates of our scheme are low enough that the data is recoverable months after being stored. Compared to prior work, our technique provides 24x and 50x higher encoding and decoding throughput and doubles the capacity, while being 37x more power efficient

Cross-Layer Optimization Techniques for Improving Performance and Reliability of NAND Flash-Based Storage Systems

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 8. 김지홍.As the cost-per-bit of NAND flash memory is quickly improved by advanced process technologies and multi-leveling techniques, NAND flash-based storage systems are widely employed from mobile embedded systems to high-end enterprise server systems. Although the advanced process and device techniques have greatly improved the cost-per-bit of NAND flash memory, they have also significantly degraded the performance and reliability of NAND flash memory as key side effects of the advanced techniques. In order for NAND flash-based storage systems to be more broadly used in various computing environments, it is critical to overcome the performance and reliability problems of recent high-density NAND flash memory in a satisfactory fashion. In this dissertation, we argue that cross-layer optimization techniques, which vertically integrate various optimization factors from different design abstraction levels, can play key roles in improving performance and reliability of high-density NAND flash memory. First, we propose read-disturb management techniques which reduce the expensive read-disturb management overheads while maintaining reliability of NAND flash memory. An FTL using the read-disturb management module, called redFTL, alleviates highly skewed read accesses to a small part of NAND flash memory into more balanced read accesses to a large number of blocks, thus reducing data migrations needed for avoiding read-disturb errors. As an extended version of redFTL, we propose an integrated read-disturb management technique, called redFTL+, which fundamentally solves read-disturb problems by exploiting a tradeoff between the read disturbance and write speed. By modifying NAND chips to support multiple read modes with different read voltages and write speeds, redFTL+ intelligently allocates frequently-read data to read-resistant blocks. Since the read disturbance is also proportional to the read time, redFTL+ takes advantage of the difference in the read time among different NAND pages by reallocating read-intensive data to read-resistant pages. Second, we propose data separation techniques which reduce garbage collection overhead. We propose a program context-aware data separation technique, called PDS, which can reduce the garbage collection overhead by exploiting program context hints. By using a program context, which serves as a proper granularity of maintaining data update behavior, PDS helps an FTL gather data with similar update times to the same blocks. As an improved version of PDS, we propose an integrated data separation technique, called IDS, which uses both update history of NAND device and program context hints for predicting data update behaviors. By classifying data based on the cross-layer information, an FTL using IDS can make more dead or near-dead blocks over PDS, thus reducing the garbage collection overhead. In order to evaluate the effectiveness of the proposed techniques, we performed a series of evaluations using both a simulator and an emulator with I/O traces which were collected from various systems. Our experimental results show that cross-layer optimization techniques are more effective over our single-layer optimization techniques. RedFTL+ decreases the read-disturb management overhead on average by 24% over redFTL. The IDS-based FTL decreases the garbage collection overhead on aver-age by 18% over the PDS-based FTL. The evaluation results demonstrate that our cross-layer optimization techniques improve an overall performance of NAND-based storage systems over previous single-layered optimization techniques by reducing overheads from read-disturb management and garbage collection while maintaining the reliability of the storage systems.Contents I. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Read-Disturb Problem . . . . . . . . . . . . . . . . 2 1.1.2 Garbage Collection Problem . . . . . . . . . . . . . 4 1.2 Research Goals and Contributions . . . . . . . . . . . . . . 7 1.3 Dissertation Structure . . . . . . . . . . . . . . . . . . . . . 9 II. Background . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 NAND Flash Memory . . . . . . . . . . . . . . . . . . . . 11 2.2 System Software for NAND Flash Memory . . . . . . . . . 17 2.3 NAND Flash-Based Storage Devices . . . . . . . . . . . . . 18 2.4 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.1 Read-Disturb Techniques . . . . . . . . . . . . . . . 20 2.4.2 Data Separation Techniques . . . . . . . . . . . . . 21 III. A Single-Layered Read Disturb Management Technique . . . 24 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 Performance Implications of Read Disturbs . . . . . . . . . 28 3.2.1 Effect of Frequent Read Reclaims . . . . . . . . . . 28 3.2.2 Effect of Read Reclaims on Response Time Fluctu- ations . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.3 Effect of SSD Read Buffer on Read Reclaims . . . . 31 3.3 Read Disturb Management Techniques . . . . . . . . . . . . 32 3.3.1 Data Distribution Technique . . . . . . . . . . . . . 32 3.3.2 Proactive Data Migration . . . . . . . . . . . . . . . 35 3.4 RedFTL: Read Disturb-Aware FTL . . . . . . . . . . . . . . 35 3.4.1 Overview of RedFTL . . . . . . . . . . . . . . . . . 35 3.4.2 Read-Hot Page Separation . . . . . . . . . . . . . . 37 3.4.3 Good Block Pool Management . . . . . . . . . . . . 38 3.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . 38 IV. An Integrated Approach for Read Disturb Management . . . 43 4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 Read Disturb Management Techniques . . . . . . . . . . . . 46 4.2.1 Mitigation of Read Reclaims by Read Voltage Scaling 47 4.2.2 Mitigation of Read Reclaims by Read Operation Time Scaling . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2.3 NAND Read-Disturbance Model . . . . . . . . . . . 55 4.3 Design and Implementation of RedFTL+ . . . . . . . . . . . 57 4.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . 57 4.3.2 Dynamic Mode Selection . . . . . . . . . . . . . . . 58 4.3.3 Distributed Migration to RRBs . . . . . . . . . . . . 59 4.3.4 Read-Hotness Detection . . . . . . . . . . . . . . . 61 4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . 63 V. A Single-Layered Data Separation Technique . . . . . . . . . 70 5.1 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.1.1 Frequency-Based Data Separation . . . . . . . . . . 70 5.1.2 Garbage Collection Using ORA . . . . . . . . . . . 73 5.1.3 Evaluation of Existing Locality-based Heuristic . . . 74 5.2 Correlation between Program Contexts and Updates . . . . 78 5.3 PDS: Program Context-Aware Data Separation Technique . . 82 5.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . 87 VI. An Integrated Data Separation Technique . . . . . . . . . . . 93 6.1 Limitations of Single-Layered Program Context-Aware Data Separation Technique . . . . . . . . . . . . . . . . . . . . . 93 6.2 IDS: Integrated Data Separation Technique . . . . . . . . . 94 6.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . 94 6.2.2 Determination of Update Program Context . . . . . 96 6.2.3 Dynamic Clustering Program Contexts Based On Update Locality . . . . . . . . . . . . . . . . . . . . 96 6.2.4 Managing The Hot Data Associated with An Update Program Context . . . . . . . . . . . . . . . . 103 6.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . 104 VII. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.2.1 Improving QoS of RedFTL+ by Exploiting Program Context Hints . . . . . . . . . . . . . . . . . . 114 7.2.2 Mitigating Read-Disturb Problem by Read Disturb- Aware Read Buffer Management Technique . . . . . 115 7.2.3 Improving Efficiency of Garbage Collection by Adjusting GC Trigger Points . . . . . . . . . . . . . . 115 7.2.4 Improving Performance and Reliability of NAND Flash Memory by Integrating Various Techniques . . 117 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Docto

Stash in a Flash

Encryption is a useful tool to protect data confidentiality. Yet it is still challenging to hide the very presence of encrypted, secret data from a powerful adversary. This paper presents a new technique to hide data in flash by manipulating the voltage level of pseudo-randomlyselected flash cells to encode two bits (rather than one) in the cell. In this model, we have one “public” bit interpreted using an SLC-style encoding, and extract a private bit using an MLC-style encoding. The locations of cells that encode hidden data is based on a secret key known only to the hiding user. Intuitively, this technique requires that the voltage level in a cell encoding data must be (1) not statistically distinguishable from a cell only storing public data, and (2) the user must be able to reliably read the hidden data from this cell. Our key insight is that there is a wide enough variation in the range of voltage levels in a typical flash device to obscure the presence of fine-grained changes to a small fraction of the cells, and that the variation is wide enough to support reliably re-reading hidden data. We demonstrate that our hidden data and underlying voltage manipulations go undetected by support vector machine based supervised learning which performs similarly to a random guess. The error rates of our scheme are low enough that the data is recoverable months after being stored. Compared to prior work, our technique provides 24x and 50x higher encoding and decoding throughput and doubles the capacity, while being 37x more power efficient