4 research outputs found
Property-Driven Fence Insertion using Reorder Bounded Model Checking
Modern architectures provide weaker memory consistency guarantees than
sequential consistency. These weaker guarantees allow programs to exhibit
behaviours where the program statements appear to have executed out of program
order. Fortunately, modern architectures provide memory barriers (fences) to
enforce the program order between a pair of statements if needed. Due to the
intricate semantics of weak memory models, the placement of fences is
challenging even for experienced programmers. Too few fences lead to bugs
whereas overuse of fences results in performance degradation. This motivates
automated placement of fences. Tools that restore sequential consistency in the
program may insert more fences than necessary for the program to be correct.
Therefore, we propose a property-driven technique that introduces
"reorder-bounded exploration" to identify the smallest number of program
locations for fence placement. We implemented our technique on top of CBMC;
however, in principle, our technique is generic enough to be used with any
model checker. Our experimental results show that our technique is faster and
solves more instances of relevant benchmarks as compared to earlier approaches.Comment: 18 pages, 3 figures, 4 algorithms. Version change reason : new set of
results and publication ready version of FM 201
A Verification-Based Approach to Memory Fence Insertion in PSO Memory Systems
peer reviewedThis paper addresses the problem of verifying and correcting programs when they
are moved from a sequential consistency execution environment to a relaxed
memory context. Specifically, it considers the PSO (Partial Store Order)
memory model, which corresponds to the use of a store buffer for each shared
variable and each process. We also will consider, as an intermediate step, the
TSO (Total Store Order) memory model, which corresponds to the use of one store
buffer per process.
The proposed approach extends a previously developed verification tool that uses
finite automata to symbolically represent the possible contents of the store
buffers. Its starting point is a program that is correct for the usual
Sequential Consistency (SC) memory model, but that might be incorrect under PSO with
respect to safety properties.
This program is then first analyzed and corrected for the TSO memory model, and
then this TSO-safe program is analyzed and corrected under PSO, producing a
PSO-safe program. To obtain a TSO-safe program, only store-load fences (TSO
only allows store-load relaxations) are introduced into the program. Finaly, to
produce a PSO-safe program, only store-store fences (PSO
additionally allows store-store relaxations) are introduced.
An advantage of our technique is that the underlying symbolic verification tool
makes a full exploration of program behaviors possible even for cyclic
programs, which makes our approach broadly applicable. The method has been
tested with an experimental implementation and can effectively handle a series
of classical examples
Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021
The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing