AN APPROACH TOWARDS EFFICIENT VIDEO DATA HIDING USING PROHIBITED ZONE

The process of embedding information into a host medium is a data hiding. In general, due to their wide presence and the tolerance of human perceptual systems involved visual and arual media are preferred. The methods vary depending on the nature of such media and the general structure of data hiding process does not depend on the host media type. Due to the design complexities involved video data hiding is still an important research topic. A new video data hiding method that makes use of removal correction capabilities of replicate accumulate codes and advantage of prohibited zone data hiding is proposed in this paper. To determine host signal samples suitable for data hiding selective embedding is utilized in the proposed method. In order to withstand frame drop and insert attacks a temporal synchronization scheme is contained in this method. By typical broadcast material against MPEG- 2, H.264 compression, frame-rate renovation attacks, as well as other renowned video data hiding methods the proposed framework is tested here. For typical system parameters the decoding error values are reported. The imitation results specify that the frame can be effectively utilized in video data hiding applications

Multi-Power Irregular Repetition Slotted ALOHA in Heterogeneous IoT networks

International audienceIrregular Repetition Slotted Aloha (IRSA) is one candidate member of a family of random access protocols to provide solutions for massive parallel connections in the Internet of Things (IoT) networks. The key features of this protocol are repeating the transmitted packets several times and using Successive Interference Cancellation (SIC) at the decoder to resolve the collisions, which dramatically increases the performance of Slotted ALOHA. Motivated by multiple previous studies of IRSA performance in different settings, we focus on the scenario of an IoT network where the packets of different nodes are received with different powers at the base station, either per design due to different transmission power, or induced by the fact that the nodes are at different distances from the base station. In such a scenario, the capture effect emerges at the receiver, which in turn enhances the protocol performance. We analyze the protocol behavior using a new density evolution which is based on dividing nodes into classes with different powers. By computing the probability to decode a packet in the presence of the interference, we explore the achievable throughput and its associated gain and show the excellent performance of Multi-Power IRSA

New Algorithms for High-Throughput Decoding with Low-Density Parity-Check Codes using Fixed-Point SIMD Processors

Most digital signal processors contain one or more functional units with a single-instruction, multiple-data architecture that supports saturating fixed-point arithmetic with two or more options for the arithmetic precision. The processors designed for the highest performance contain many such functional units connected through an on-chip network. The selection of the arithmetic precision provides a trade-off between the task-level throughput and the quality of the output of many signal-processing algorithms, and utilization of the interconnection network during execution of the algorithm introduces a latency that can also limit the algorithm\u27s throughput. In this dissertation, we consider the turbo-decoding message-passing algorithm for iterative decoding of low-density parity-check codes and investigate its performance in parallel execution on a processor of interconnected functional units employing fast, low-precision fixed-point arithmetic. It is shown that the frequent occurrence of saturation when 8-bit signed arithmetic is used severely degrades the performance of the algorithm compared with decoding using higher-precision arithmetic. A technique of limiting the magnitude of certain intermediate variables of the algorithm, the extrinsic values, is proposed and shown to eliminate most occurrences of saturation, resulting in performance with 8-bit decoding nearly equal to that achieved with higher-precision decoding. We show that the interconnection latency can have a significant detrimental effect of the throughput of the turbo-decoding message-passing algorithm, which is illustrated for a type of high-performance digital signal processor known as a stream processor. Two alternatives to the standard schedule of message-passing and parity-check operations are proposed for the algorithm. Both alternatives markedly reduce the interconnection latency, and both result in substantially greater throughput than the standard schedule with no increase in the probability of error