2 research outputs found

    Simulation and Analysis of Flying Adder Frequency Synthesizer Combined with LFSR

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    [[abstract]]本論文主要是改善在2002年Hugh Mair及Liming Xiu所提出的“高效益頻率合成器”為基礎,並結合於2011年Liming Xiu提出的“飛加器頻率合成器基於隨機進位方式降低分數突波”的方法,我們將利用線性反饋移位暫存器(LFSR)具隨機儲存裝置,並將該裝置結合飛加器頻率合成器並以HSPICE模擬,再行分析。 論文第二章、第三章是分析低頻33 33MHz、高頻117 75MHz傳統型飛加器頻率合成器差異以及飛加器頻率合成器具LFSR 15state、飛加器頻率合成器具LFSR 16state的比較與理想DCO電路與實際DCO電路的數據比較,在相互整體數據分析下得知在低頻33 33MHz LFSR 15state改善後平均差值為33 88 dB、16state改善後平均差值為38 97 dB 與高頻117 75MHz LFSR 15state改善後平均差值45 69 dB、16state改善後平均差值40 12 dB共四種的數據都顯示高於Cout平均差值25 41 dB由此可知在抑制分數突刺有明顯的效果。 第四章無記憶體虛擬隨機亂數裝置(Memory less),在整體數據分析下得知在低頻33 33MHz Memory less改善後平均差值33 90 dB以及高頻117 75 MHz Memory less改善後平均差值39 48 dB的數據都顯示高於Cout平均差值25 41 dB由此可知在抑制分數突刺有明顯的效果。[[abstract]]This thesis improves the paper proposed by Hugh Mair and Liming Xiu “A Architecture of High-performance Frequency Phase Synthesis” in 2002 We also combine the method proposed by Liming Xiu’s “A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer” in 2011 We use the HSPICE to simulate the flying-adder frequency synthesizer with linear feedback shift register In chapter two and three we simulate the low frequency with 33 33MHz and high frequency with 117 75 MHz for flying-adder frequency synthesizer with LFSR 15 state and LFSR 16 state In 33 MHz’s DCO the average performance is 33 88 dB and 38 97 dB for LFSR 15 state and LFSR 16 state respectively In 117 75 MHz the average performance is 45 69 dB and 40 12 dB for LFSR 15 state and LFSR 16 state respectively All four values of performance improvement are better than 25 4 dB in traditional flying-adder frequency synthesizer Therefore the proposed method can reduce the fractional spur in traditional flying-adder frequency synthesizer The pseudo random number generator without memory is proposed in chapter 4 The memory less structure can save area and power The average performance is 33 90 dB in 33 MHz The average performance is 39 4 dB in 117 75 MHz Both average values of performance improvement are better than 25 5dB in traditional flying-adder frequency synthesizer The fractional spur has been reduced by pseudo random generator without memor

    The Research on LFSR with Pseudo Random Storage

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    [[abstract]]飛加器頻率合成器是一種新型態的頻率合成技術,係基於時間平均頻率(TAF)的概念進行頻率合成,雖然傳統飛加器頻率合成器可藉由小數控制字元(FCW)提高頻率的解析度,也因為如此傳統飛加器頻率合成器本身將會受到分數突刺的影響。 本論文探討2011 年Liming Xiu 、 Ming Lin 及Hong Jiang 提出隨機進位方式改善因小數部位累加進位值具有週期性而導致的分數突刺,因此我們利用線性反饋暫存器(LFSR)的特性研發出4bit 以及9bit LFSR 具隨機儲存的裝置,同時使用FPGA 將該裝置結合傳統飛加器頻率合成器加以實現,透過隨機進位方式改善因小數部位累加進位值具有週期性而導致的分數突刺,並且完成各種不同控制字元 下抑制分數突刺的驗證與分析。 論文最後同樣將透過時間平均頻率概念,將LFSR 具隨機儲存裝置以及一階差異積分調製器這兩種裝置實際運用於調控數位控制振盪器(DCO)晶片當中,其目的為增加DCO 頻率輸出的解析度,在透過不同的控制字元調控DCO 後,分析及驗證調控後所輸出的頻率與理論頻率的平均誤差小於0 02%,並且將兩種不同調控裝置所輸出的頻率頻譜進行比較與分析。[[abstract]]The flying-adder based frequency synthesizer architecture is a novel technique of generating frequency which is based on Time-Average-Frequency (TAF) concept to synthesis frequency Although traditional flying-adder based frequency synthesizer can be improved frequency resolution by fractional control word (FCW) However the traditional flying-adder based frequency synthesizer will be affected by fractional spurs In this thesis we investigated the paper “A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer ” in 2011 which was published by Liming Xiu Ming Lin and Hong Jiang So we propose a new architecture that we design and development of 4 bit & 9 bit Liner-Feedback-Shift-Register (LFSR) with pseudo random storage And we utilize the FPGA to implement the LFSR with pseudo random storage device and traditional flying-adder based frequency synthesizer The proposed methods of randomizing the carries reduce the spurs which are affected by the periodicity of the fractional carry We also measure the implementation under various control words for analysis and verification Finally by the concept of the Time-Average-Frequency (TAF) we utilize LFSR with pseudo random storage device and first order Delta Sigma Modulator (1st DSM) to improve the frequency resolution of Digital Control Oscillator (DCO) By various control word to control the DCO we analysis and verify the frequency error of actual frequency output which average is less than 0 02% We use the spectrum analyzer to measure and analysis the DCO’s frequency spectrum under different frequency control wor
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