D-LQF: An efficient distributed scheduling algorithm for input-queued switches

Due to the massive use of parallel and distributed operations of inputs and outputs, iterative scheduling algorithms are attractive in finding a maximal size matching for an input-queued switch. For constructing a large high-speed switch, a distributed multi-chip implementation of an iterative scheduling algorithm should be followed. Since different chips may locate on different switch linecards and linecards can be separated by tens of meters, the propagation delay between chips/linecards is non-negligible. This calls for a pipelined implementation of a single-iteration scheduling algorithm. In this paper, an efficient, pipelined single-iteration algorithm called Distributed Longest Queue First (D-LQF) is proposed. In D-LQF, exhaustive service policy is adopted for reusing the matched input-output pairs in the previous time slot. To avoid incorrectly granting an empty VOQ from transmission (caused by inter-chip latency), each output keeps track of the lengths of all VOQs destined to it. As compared with other single-iteration scheduling algorithms, extensive simulation results show that D-LQF provides the best delay-throughput performance. © 2011 IEEE.published_or_final_versionThe 2011 IEEE International Conference on Communications (ICC 2011), Kyoto, Japan, 5-9 June 2011. In Proceedings of the IEEE ICC, 2011, p. 1-

Efficient queue-balancing switch for FPGAs

This paper presents a novel FPGA-based switch design that achieves high algorithmic performance and an efficient FPGA implementation. Crossbar switches based on virtual output queues (VOQs) and variations have been rather popular for implementing switches on FPGAs, with applications to network-on-chip (NoC) routers and network switches. The efficiency of VOQs is well-documented on ASICs, though we show that their disadvantages can outweigh their advantages on FPGAs. Our proposed design uses an output-queued switch internally for simplifying scheduling, and a queue balancing technique to avoid queue fragmentation and reduce the need for memory-sharing VOQs. Our implementation approaches the scheduling performance of the state-of-the-art, while requiring considerably fewer FPGA resources

Experimental survey of FPGA-based monolithic switches and a novel queue balancer

This paper studies small to medium-sized monolithic switches for FPGA implementation and presents a novel switch design that achieves high algorithmic performance and FPGA implementation efficiency. Crossbar switches based on virtual output queues (VOQs) and variations have been rather popular for implementing switches on FPGAs, with applications in network switches, memory interconnects, network-on-chip (NoC) routers etc. The implementation efficiency of crossbar-based switches is well-documented on ASICs, though we show that their disadvantages can outweigh their advantages on FPGAs. One of the most important challenges in such input-queued switches is the requirement for iterative scheduling algorithms. In contrast to ASICs, this is more harmful on FPGAs, as the reduced operating frequency and narrower packets cannot “hide” multiple iterations of scheduling that are required to achieve a modest scheduling performance.Our proposed design uses an output-queued switch internally for simplifying scheduling, and a queue balancing technique to avoid queue fragmentation and reduce the need for memory-sharing VOQs. Its implementation approaches the scheduling performance of a state-of-the-art FPGA-based switch, while requiring considerably fewer resources

Design of a Hybrid Modular Switch

Network Function Virtualization (NFV) shed new light for the design, deployment, and management of cloud networks. Many network functions such as firewalls, load balancers, and intrusion detection systems can be virtualized by servers. However, network operators often have to sacrifice programmability in order to achieve high throughput, especially at networks' edge where complex network functions are required. Here, we design, implement, and evaluate Hybrid Modular Switch (HyMoS). The hybrid hardware/software switch is designed to meet requirements for modern-day NFV applications in providing high-throughput, with a high degree of programmability. HyMoS utilizes P4-compatible Network Interface Cards (NICs), PCI Express interface and CPU to act as line cards, switch fabric, and fabric controller respectively. In our implementation of HyMos, PCI Express interface is turned into a non-blocking switch fabric with a throughput of hundreds of Gigabits per second. Compared to existing NFV infrastructure, HyMoS offers modularity in hardware and software as well as a higher degree of programmability by supporting a superset of P4 language

Load-balanced optical switch for high-speed router design

A hybrid electro-optic router is attractive, where packet buffering and table lookup are carried out in electrical domain and switching is done optically. In this paper, we propose a loadbalanced optical switch (LBOS) fabric for a hybrid router. LBOS comprises N linecards connected by an N-wavelength WDM fiber ring. Each linecard i is configured to receive on channel λ i. To send a packet, it can select and transmit on an idle channel based on where the packet goes. The packet remains in the optical domain all the way from an input linecard/port to an output linecard/port. Meanwhile, the loading in the ring network is perfectly balanced by spreading the packets for different destinations to use different wavelengths, and packets for the same destination to use different time slots. With the pipelined operation of the LBOS, we show that LBOS is an optical counterpart of an efficient load-balanced electronic switch, and close-to-100% throughput can be obtained. To address the ringfairness problem under the inadmissible traffic patterns, an efficient throughput-fair scheduler for LBOS is also devised. ©2010 IEEE.published_or_final_versio

Feedback-based scheduling for load-balanced two-stage switches

A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unlike existing approaches, we show that the efforts made in load balancing and keeping packets in order can complement each other. Specifically, at each middle-stage port between the two switch fabrics of a load-balanced switch, only a single-packet buffer for each virtual output queueing (VOQ) is required. Although packets belonging to the same flow pass through different middle-stage VOQs, the delays they experience at different middle-stage ports will be identical. This is made possible by properly selecting and coordinating the two sequences of switch configurations to form a joint sequence with both staggered symmetry property and in-order packet delivery property. Based on the staggered symmetry property, an efficient feedback mechanism is designed to allow the right middle-stage port occupancy vector to be delivered to the right input port at the right time. As a result, the performance of load balancing as well as the switch throughput is significantly improved. We further extend this feedback mechanism to support the multicabinet implementation of a load-balanced switch, where the propagation delay between switch linecards and switch fabrics is nonnegligible. As compared to the existing load-balanced switch architectures and scheduling algorithms, our solutions impose a modest requirement on switch hardware, but consistently yield better delay-throughput performance. Last but not least, some extensions and refinements are made to address the scalability, implementation, and fairness issues of our solutions. © 2009 IEEE.published_or_final_versio

Efficient time slot assignment algorithms for TDM hierarchical and nonhierarchical switching systems

Two efficient time slot assignment algorithms, called the two-phase algorithm for the nonhierarchical and the three-phase algorithm for the hierarchical time-division multiplex (TDM) switching systems, are proposed. The simple idea behind these two algorithms is to schedule the traffic on the critical lines/trunks of a traffic matrix first. The time complexities of these two algorithms are found to be O(LN2) and O(LM2), where L is the frame length, N is the switch size, and M is the number of input/output users connected to a hierarchical TDM switch. Unlike conventional algorithms, they are fast, iterative and simple for hardware implementation. Since no backtracking is used, pipelined packet transmission and packet scheduling can be performed for reducing the scheduling complexity of a transmission matrix to O(N2) and O(M2), respectively. Extensive simulations reveal that the two proposed algorithms give close-to-optimal performance under various traffic conditions.published_or_final_versio