Design considerations for integrated continuous-time chaotic oscillators

This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.Comisión Interministerial de Ciencia y Tecnología TIC 96-1392-CO2-

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Bifurcations and synchronization using an integrated programmable chaotic circuit

This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic behaviors by changing a few external bias currents. In particular, by changing one of these bias currents, the chip provides different examples of a period-doubling route to chaos. We present experimental orbits and attractors, time waveforms and power spectra measured from the chip. By using two chip units, experiments on synchronization can be carried out as well in real-time. Measurements are presented for the following synchronization schemes: linear coupling, drive-response and inverse system. Experimental statistical characterizations associated to these schemes are also presented. We also outline the possible use of the chip for chaotic encryption of audio signals. Finally, for completeness, the paper includes also a brief description of the chip design procedure and its internal circuitry

CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Noise enhanced spontaneous chaos in semiconductor superlattices at room temperature

Physical systems exhibiting fast spontaneous chaotic oscillations are used to generate high-quality true random sequences in random number generators. The concept of using fast practical entropy sources to produce true random sequences is crucial to make storage and transfer of data more secure at very high speeds. While the first high-speed devices were chaotic semiconductor lasers, the discovery of spontaneous chaos in semiconductor superlattices at room temperature provides a valuable nanotechnology alternative. Spontaneous chaos was observed in 1996 experiments at temperatures below liquid nitrogen. Here we show spontaneous chaos at room temperature appears in idealized superlattices for voltage ranges where sharp transitions between different oscillation modes occur. Internal and external noises broaden these voltage ranges and enhance the sensitivity to initial conditions in the superlattice snail-shaped chaotic attractor thereby rendering spontaneous chaos more robust.Comment: 6 pages, 4 figures, revte

A fully CMOS true random number generator based on hidden attractor hyperchaotic system

Low-power devices used in Internet-of-things networks have been short of security due to the high power consumption of random number generators. This paper presents a low-power hyperchaos-based true random number generator, which is highly recommended for secure communications. The proposed system, which is based on a four-dimensional chaotic system with hidden attractors and oscillators, exhibits rich dynamics. Numerical analysis is provided to verify the dynamic characteristics of the proposed system. A fully customized circuit is deployed using 130 nm CMOS technology to enable integration into low-power devices. Four output signals are used to seed a SHIFT-XOR-based chaotic data post-processing to generate random bit output. The chip prototype was simulated and tested at 100 MHz sampling frequency. The hyperchaotic circuit consumes a maximum of 980 μ W in generating chaotic signals while dissipates a static current of 623 μ A. Moreover, the proposed system provides ready-to-use binary random bit sequences which have passed the well-known statistical randomness test suite NIST SP800-22. The proposed novel system design and its circuit implementation provide a best energy efficiency of 4.37 pJ/b at a maximum sampling frequency of 100 MHz