Modeling and design of high speed SRAM based memory chip

SRAM is used as Cache memory which is very fast and used to speed up the task of processor and memory interface. With improvements in VLSI technology, processor speeds have increased. The improvements in SRAM speed of operation with increased integration, bigger sizes, technology shrinking and power dissipation is required to match with improved processor. 2kb SRAM block is designed and tested for proper read and write operation. The single SRAM cell, the 32x32 memory array, along with the decoder circuit, the sense enable and write enable logic, are placed out. The different critical paths of the system, comprising of the row and the column decoder, the column mux and the read-write circuits are recognized and sized to meet the target specifications. Simple model for distributed interconnect delays, is introduced and verified by Cadence simulations, their necessity is demonstrated. The models for the delay of a SRAM are used to determine the array sizes for a SRAM. An analytical delay model is proposed to predict the block size for SRAM; proposed model is based on dynamic strategies for word line charging and bit line discharging. Novel Sense Amplifier (SA) circuit for 2kb SRAM is presented and analyzed in this work. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of the current controlled SA. Butterfly architecture that is central decoding scheme is used to make a 2kb block from 1kb, after simulations, the maximum operating frequency of the system was found to be 800MHz

A Resilient and Power Efficient Automatic-Power-Down Sense Amplifier for SRAM Design

[[abstract]]A conventional latch-type sense amplifier in a static random access memory (SRAM) could trigger sensing failure under severe process variation. On the other hand, a traditional current-mirror sense amplifier could consume too much power. To strike a good balance, this paper presents an automatic-power-down (APD) sense amplifier, which can avoid sensing failure while keeping the power dissipation low. In this scheme, the operation window of the sense amplifier is adaptive to the real silicon speed of its associated column through Schmitt-Trigger-based dual-V HL APD circuitry. A 64-kb SRAM design using the proposed technique in a 22-nm predictive technology model demonstrates that a power savings of 28%-87% over the traditional current-mirror sense amplifier is achievable.[[fileno]]2030116010026[[department]]電機工程學

Design of High Performance SRAM Based Memory Chip

The semiconductor memory SRAM uses bi-stable latch circuit to store the logic data 1 or 0. It differs from Dynamic RAM (DRAM) which needs periodic refreshment operation for the storage of logic data. Depending upon the frequency of operation SRAM power consumption varies i.e. it consumes very high power at higher frequencies like DRAM. The Cache memory present in the microprocessor needs high speed memory hence SRAM can be used for that purpose in microprocessors. The DRAM is normally used in the Main memory of processors, where importance is given to the density than its speed. The SRAM is also used in industrial subsystems, scientific and automotive electronics. In this thesis 16-Kb Memory is designed by using memory banking method in UMC 90nm technology ,which operates at a frequency of 1GHz.The post layout simulation for the complete design is performed and also obtained power analysis for the overall design. All peripherals like pre-charge, Row Decoder, Word line driver, Sense amplifier, Column Decoder/Mux and write driver are designed and layouts of all the above peripherals also drawn in an optimised manner such that their layout occupies minimum area. The 6T SRAM cell is designed with operating frequency of 8 GHz and stability analysis are also performed for single SRAM cell. The layout of Single SRAM cell is drawn in a symmetric manner, such that two adjacent cells can share same contact, which results reduction in the area of cell layout. The Static Noise Margin, Read noise margin and Write Noise Margin of single cell are found to be 240mV, 115mV and 425mV respectively for a supply voltage of 1V.The effect of pull-up ratio and cell ratio on the stability of SRAM cell is observed