Intelligent intrusion detection in low power IoTs

Security and privacy of data are one of the prime concerns in today’s Internet of Things (IoT). Conventional security techniques like signature-based detection of malware and regular updates of a signature database are not feasible solutions as they cannot secure such systems effectively, having limited resources. Programming languages permitting immediate memory accesses through pointers often result in applications having memory-related errors, which may lead to unpredictable failures and security vulnerabilities. Furthermore, energy efficient IoT devices running on batteries cannot afford the implementation of cryptography algorithms as such techniques have significant impact on the system power consumption. Therefore, in order to operate IoT in a secure manner, the system must be able to detect and prevent any kind of intrusions before the network (i.e., sensor nodes and base station) is destabilised by the attackers. In this article, we have presented an intrusion detection and prevention mechanism by implementing an intelligent security architecture using random neural networks (RNNs). The application’s source code is also instrumented at compile time in order to detect out-of-bound memory accesses. It is based on creating tags, to be coupled with each memory allocation and then placing additional tag checking instructions for each access made to the memory. To validate the feasibility of the proposed security solution, it is implemented for an existing IoT system and its functionality is practically demonstrated by successfully detecting the presence of any suspicious sensor node within the system operating range and anomalous activity in the base station with an accuracy of 97.23%. Overall, the proposed security solution has presented a minimal performance overhead.</jats:p

On the road with third-party apps: Security analysis of an in-vehicle app platform

Digitalization has revolutionized the automotive industry. Modern cars are equipped with powerful Internetconnected infotainment systems, comparable to tablets and smartphones. Recently, several car manufacturers have announced the upcoming possibility to install third-party apps onto these infotainment systems. The prospect of running third-party code on a device that is integrated into a safety critical in-vehicle system raises serious concerns for safety, security, and user privacy. This paper investigates these concerns of in-vehicle apps. We focus on apps for the Android Automotive operating system which several car manufacturers have opted to use. While the architecture inherits much from regular Android, we scrutinize the adequateness of its security mechanisms with respect to the in-vehicle setting, particularly affecting road safety and user privacy. We investigate the attack surface and vulnerabilities for third-party in-vehicle apps. We analyze and suggest enhancements to such traditional Android mechanisms as app permissions and API control. Further, we investigate operating system support and how static and dynamic analysis can aid automatic vetting of in-vehicle apps. We develop AutoTame, a tool for vehicle-specific code analysis. We report on a case study of the countermeasures with a Spotify app using emulators and physical test beds from Volvo Cars

Reconfigurable Mobile Multimedia Systems

This paper discusses reconfigurability issues in lowpower hand-held multimedia systems, with particular emphasis on energy conservation. We claim that a radical new approach has to be taken in order to fulfill the requirements - in terms of processing power and energy consumption - of future mobile applications. A reconfigurable systems-architecture in combination with a QoS driven operating system is introduced that can deal with the inherent dynamics of a mobile system. We present the preliminary results of studies we have done on reconfiguration in hand-held mobile computers: by having reconfigurable media streams, by using reconfigurable processing modules and by migrating functions

FDMA Enabled Phase-based Wireless Network-on-Chip using Graphene-based THz-band Antennas

The future growth in System-on-chip design is moving in the direction of multicore systems. Design of efficient interconnects between cores are crucial for improving the performance of a multicore processor. Such trends are seen due to the benefits the multicore systems provide in terms of power reduction and scalability. Network-on-chips (NoC) are viewed as an emerging solution in the design of interconnects in multicore systems. However, Traditional Network-on-chip architectures are no longer able to satisfy the performance requirements due to long distance communication over multi-hop wireline paths. Multi-hop communication leads to higher energy consumption, increase in latency and reduction in bandwidth. Research in recent years has explored emerging technologies such as 3D integration, photonic and radio frequency based Network-on-chips. The use of wireless interconnects using mm-wave antennas are able to alleviate the performance issues in a wireline interconnect system. However, to satisfy the increasing demand for higher bandwidth and lower energy consumption, Wireless Network-on-Chip enabled with high speed direct links operating in THz band between distant cores is desired. Recent research has brought to light highly efficient graphene-based antennas operating in THz band. These antennas can provide high data rate and are found to consume less power with low area overheads. In this thesis, an innovative approach using novel devices based on graphene structures is proposed to provide a high-performance on-chip interconnection. This novel approach combines the regular NoC structure with the proposed wireless infrastructure to exploit the performance benefits. An architecture with wireless interfaces on every core is explored in this work. Simultaneous multiple communications in a network can be achieved by adopting Frequency Division Multiple access (FDMA). However, in a system where all cores are equipped with a wireless interface, FDMA requires more number of frequency bands. This becomes difficult to achieve as the system scales and the number of cores increase. Therefore, a FDMA protocol along with a 4-phased repetitive multi-band architecture is envisioned in this work. The phase-based protocol allows multiple wireless links to be active at a time, the phase-based protocol along with the FDMA protocol provides a reliable data transfer between cores with lesser number of frequency bands. In this thesis, an architecture with a combination of FDMA and phase-based protocol using point-to-point graphene-based wireless links is proposed. The proposed architecture is also extended for a multichip system. With cycle accurate system-level simulations, it is shown that the proposed architecture provides huge gains in performance and energy-efficiency in data transfer both in NoC based multicore and multichip systems

Performance Evaluation of Microservices Architectures using Containers

Microservices architecture has started a new trend for application development for a number of reasons: (1) to reduce complexity by using tiny services; (2) to scale, remove and deploy parts of the system easily; (3) to improve flexibility to use different frameworks and tools; (4) to increase the overall scalability; and (5) to improve the resilience of the system. Containers have empowered the usage of microservices architectures by being lightweight, providing fast start-up times, and having a low overhead. Containers can be used to develop applications based on monolithic architectures where the whole system runs inside a single container or inside a microservices architecture where one or few processes run inside the containers. Two models can be used to implement a microservices architecture using containers: master-slave, or nested-container. The goal of this work is to compare the performance of CPU and network running benchmarks in the two aforementioned models of microservices architecture hence provide a benchmark analysis guidance for system designers.Comment: Submitted to the 14th IEEE International Symposium on Network Computing and Applications (IEEE NCA15). Partially funded by European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No 639595) - HiEST Projec

Architectures for Wireless Sensor Networks

Various architectures have been developed for wireless sensor networks. Many of them leave to the programmer important concepts as the way in which the inter-task communication and dynamic reconfigurations are addressed. In this paper we describe the characteristics of a new architecture we proposed - the data-centric architecture. This architecture offers an easy way of structuring the applications designed for wireless sensor nodes that confers them superior performances

Energy-efficient pipelined bloom filters for network intrusion detection

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