A comparative study of novel variable set multiplier scheme and other column compression multipliers

The extensive use of multipliers in high-performance processors has been driving the demand for low-power, high-speed multipliers. This report presents a novel fast multiplier scheme that performs reduction based on non-uniform grouping in the partial product matrix. In every stage, the partial products are grouped into sets of variable heights before reduction. The algorithm is presented and compared with Wallace, Dadda, and Reduced Area Multipliers in terms of gate complexity, delay, interconnects and power utilization for 4-bit, 7-bit, 8-bit and 12-bit versions. The proposed design is observed to have a gate count of 3% lower than Wallace multipliers, comparable to Dadda in most of the cases but slightly higher than Reduced Area multipliers. To fulfill the study, a 12-bit version of each multiplier was implemented in structural Verilog with basic gates and synthesized using Xilinx Vivado. The net cell usage statistics and the power utilization values were extracted and compared. It was observed that the proposed design has better power efficiency than the other multipliers for the examined cases.Electrical and Computer Engineerin

Wallace Tree Multiplier Designs: A Performance Comparison Review

Multiplication process is often used in digital signal processing systems, microprocessors designs, communication systems, and other application specific integrated circuits. Multipliers are complex units and play an important role in deciding the overall area, speed and power consumption of digital designs. This paper presents a comparison review of various Wallace tree multiplier designs in terms of parameters like latency, complexity and power consumption. Keywords: Booth Recoding Algorithm, Carry Look Ahead Adder, Carry Select Adder, Compressors, Ripple Carry Adder, Sklansky Adder, Wallace Tree Multipliers

Towards Verifying Nonlinear Integer Arithmetic

We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give n^{O(1)} size regular resolution proofs for arbitrary degree 2 identities on array, diagonal, and Booth multipliers and quasipolynomial- n^{O(\log n)} size proofs for these identities on Wallace tree multipliers.Comment: Expanded and simplified with improved result

Low-Power, Low-Cost, & High-Performance Digital Designs : Multi-bit Signed Multiplier design using 32nm CMOS Technology

Binary multipliers are ubiquitous in digital hardware. Digital multipliers along with the adders play a major role in computing, communicating, and controlling devices. Multipliers are used majorly in the areas of digital signal and image processing, central processing unit (CPU) of the computers, high-performance and parallel scientific computing, machine learning, physical layer design of the communication equipment, etc. The predominant presence and increasing demand for low-power, low-cost, and high-performance digital hardware led to this work of developing optimized multiplier designs. Two optimized designs are proposed in this work. One is an optimized 8 x 8 Booth multiplier architecture which is implemented using 32nm CMOS technology. Synthesis (pre-layout) and post-layout results show that the delay is reduced by 24.7% and 25.6% respectively, the area is reduced by 5.5% and 15% respectively, the power consumption is reduced by 21.5% and 26.6% respectively, and the area-delay-product is reduced by 28.8% and 36.8% respectively when compared to the performance results obtained for the state-of-the-art 8 x 8 Booth multiplier designed using 32nm CMOS technology with 1.05 V supply voltage at 500 MHz input frequency. Another is a novel radix-8 structure with 3-bit grouping to reduce the number of partial products along with the effective partial product reduction schemes for 8 x 8, 16 x 16, 32 x 32, and 64 x 64 signed multipliers. Comparing the performance results of the (synthesized, post-layout) designs of sizes 32 x 32, and 64 x 64 based on the simple novel radix-8 structure with the estimated performance measurements for the optimized Booth multiplier design presented in this work, reduction in delay by (2.64%, 0.47%) and (2.74%, 18.04%) respectively, and reduction in area-delay-product by (12.12%, -5.17%) and (17.82%, 12.91%) respectively can be observed. With the use of the higher radix structure, delay, area, and power consumption can be further reduced. Appropriate adder deployment, further exploring the optimized grouping or compression strategies, and applying more low-power design techniques such as power-gating, multi-Vt MOS transistor utilization, multi-VDD domain creation, etc., help, along with the higher radix structures, realizing the more efficient multiplier designs

Design of Wallace Tree Multiplier with Power Efficient Adiabatic Logic

The objective of this project is to design high performance arithmetic circuits which are faster and have lower power consumption using a new adiabatic logic family of CMOS and to analyze its performance for sequential circuits and effects upon cascading. It commencement on evaluation of a computational block before its evaluation phase begins, and quickly performs a final evaluation as soon as the inputs are valid. This adiabatic logic family is best suited to arithmetic circuits because the critical path is made of a long chain of cascaded inverting gates.In this paper we are going to design Wallace Tree Multiplier using full adder structure with adiabatic logic. As the major advantage of this logic which is higher speed and low power consumption is observed upon cascading, it is most suitable for arithmetic circuits

Design and Analysis of High Speed Multiply and Accumulation Unit for Digital Signal Processing Applications

Unit for Digital Signal Processing Applications   Kausar Jahan1, Pala Kalyani2, V Satya Sai3, GRK Prasad4, Syed Inthiyaz5, Sk Hasane Ahammad6 1Department of ECE, Dadi Institute of Engineering and Technology Anakapalle, Andhra Pradesh, India 2Department of ECE, Vardhaman College of Engineering Kacharam, Shamshabad, India 3Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502 4Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502 5Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502 6Department of ECE, Koneru Lakshmaiah Education Foundation Guntur, India-522502   Abstract—The fundamental component used in many of the Digital signal Processing (DSP) applications are Multiply and Accumulation Unit (MAC). In the literature, a multiplier consists of greater number of full adders and half adder in partial product reduction stage, which increases the hardware complexity and critical path delay to MAC unit. To overcome this problem, two novel multipliers are proposed in this article. The proposed multipliers are designed and implemented in hardware, which reduces the circuit complexity and improves the overall performance of the MAC unit with less delay. The proposed multipliers are compared with the 4-bit existing designs and observed that the number of slices Look Up Tables (LUTs) are minimized from 113 to 43, Slices are reduced from 46 to 14, Full Adders (FAs) are lessened from 28 to 23, bonded Input Output Blocks (IOBs) and Half Adders (HAs) were not altered. The time delay is reduced from 14.251ns to 7.876ns. The proposed multipliers are compared in the literature with the 8-bit multiplier, then the number of Slice LUTs are reduced from 510 to 231, Slices are reduced from 218 to 113, FAs are reduced from 120 to 110, HAs are reduced from 56 to 39, time delay is reduced from 26.228ns to12.748ns, but bonded IOBs count remains same. The synthesis and simulations results are verified by using Xilinx ISE 14.7 version tool