A receiver with in-band IIP3>20dBm, exploiting cancelling of OpAmp finite-gain-induced distortion via negative conductance

Highly linear CMOS radio receivers increasingly exploit linear RF V-I conversion and passive down-mixing, followed by an OpAmp based Transimpedance Amplifier at baseband. Due to the finite OpAmp gain in wideband receivers operating with large signals, virtual ground is imperfect, inducing distortion currents. We propose to apply a negative conductance to cancel this distortion. In an RF receiver, this increases In-Band IIP3 from 9dBm to >20dBm, at the cost of 1.5dB extra NF and <10% power penalty. In 1MHz bandwidth, a Spurious-Free Dynamic Range of 85dB is achieved at <27mA up to 2GHz for 1.2V supply voltage

Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

Cancellation of OpAmp virtual ground imperfections by a negative conductance applied to improve RF receiver linearity

High linearity CMOS radio receivers often exploit linear V-I conversion at RF, followed by passive down-mixing and an OpAmp-based Transimpedance Amplifier at baseband. Due to nonlinearity and finite gain in the OpAmp, virtual ground is imperfect, inducing distortion currents. This paper proposes a negative conductance concept to cancel such distortion currents. Through a simple intuitive analysis, the basic operation of the technique is explained. By mathematical analysis the optimum negative conductance value is derived and related to feedback theory. In- and out-of-band linearity, stability and Noise Figure are also analyzed. The technique is applied to linearize an RF receiver, and a prototype is implemented in 65 nm technology. Measurement results show an increase of in-band IIP3 from 9dBm to >20dBm, and IIP2 from 51 to 61dBm, at the cost of increasing the noise figure from 6 to 7.5dB and <10% power penalty. In 1MHz bandwidth, a Spurious-Free Dynamic Range of 85dB is achieved at <27mA up to 2GHz for 1.2V supply voltage

A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

1.2 Racing Down the Slopes of Moore's Law

Since its inception, Moore's Law has been the driving force for IC design. Although during the first decade, 'everything' seemed to be better, however, we lost the scaling of processor clock speed and RF transistor speed, and now it looks as if power efficiency of digital gates will stall. What remains is scaling in transistor count and cost-per-function, thanks to 3D integration.Thus, this is an excellent moment to reconsider how we design for analog and digital signal processing. The higher the required signal-to-noise ratio (SNR), the more power-efficient digital signal processing is compared to analog. Pure analog processing remains more efficient only for ~ 30 dB SNR or less. In the case of digital processing, the conversion from analog to digital should therefore be made as early in the signal chain as possible. Thanks to the figure-of-merit race, analog-to-digital converters (ADCs) have experienced a tremendous win in power efficiency. However, these ADCs require a large input voltage swing while the input signals to be converted, from an antenna or sensor interface, are usually much smaller. Therefore, RF and analog front-ends are needed, which consume much more power than the ADCs to be driven.Let us re-think these analog front-ends. Can we still efficiently design these front-ends in future CMOS? Do we need so much linear amplification? Do we need active linear circuits at all? Can we not use 'digital' components to replace the analog front-ends and ADCs? This paper aims to look at digital and analog processing trends from technology and design fundamentals points of view. We will first zoom out on asymptotic trends in technology scaling and try to identify future design opportunities and challenges. For circuit design, fundamental limits linking power, speed, and accuracy will be reviewed to gain insight into the implications of how we design circuits the way we currently do. This paper aims to create awareness and gives a new vision of designing analog circuits.</p

Ultra-wideband and highly linear 43-97 GHz receiver front-end

This research presents a wideband mmWave receiver front-end that covers the frequency range from 43 to 97 GHz, supporting the operation in the major parts of the V-, E- and W-bands. The front-end incorporates a passive mixer-first topology to achieve high linearity and wideband performance along with an optimum operational instantaneous bandwidth. In addition, it implements the multi-gate gm3 cancellation technique at the IF amplifiers to preserve the linearity and provide gain at the IF section. Image rejection capabilities using a current mode transformer based IF 90o coupler is implemented on chip and demonstrated with measurements. The front-end is fabricated on the Globelfoundries 22nm FD-SOI CMOS process and demonstrates an ultra-wideband performance across the frequency range 43-97 GHz (2.25:1 bandwidth) with image rejection of up to 32 dB, IIP3 of 1.6-5.2 dBm and gain of 15 dB. Furthermore, the measurement results show that the front-end supports high speed modulated signals of up to 6 Gbps 64QAM modulation data.M.S