A novel multiple-valued CMOS flip-flop employing multiple-valued clock.

A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterised by improved storage capacity, flexible logic structure and reduced power dissipation