An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

Digital subsystem prefers CMOS process, but it is difficult to manage speed and average power (Pavg) trade-off in each era with power supply voltage (Vdd) scaling. Current mode logic (CML) has emerged as an alternative to design the fundamental block of a SerDes, namely, the latch. However, available CML circuits consume significant Pavg and suffer from rapid input slewing. Typically, fast switching inputs enable current flow to effective supply voltage VP and overcharges output. In fact, VP is different than externally applied Vdd and oscillates with time as and when an abrupt current is drawn. This affects delay td and introduces jitter. The topic presents a new latch for SerDes interface using a new current steering circuit and coupled to a power delivery network (PDN). The significant point is to attain an almost constant td in comparison to conventional designs while the Vdd changes. The post-layout results at 0.09-μm CMOS and 1.1 V Vdd indicate that the Pavg and td are 339.5 µW and 61.9 ps, respectively, at 27OC. Surprisingly, the td variation is noted to be minimum and the power supply noise induced jitter is around 1.5 ns when VP close to the circuit varies due to sudden current

Enhanced Hardware Security Using Charge-Based Emerging Device Technology

The emergence of hardware Trojans has largely reshaped the traditional view that the hardware layer can be blindly trusted. Hardware Trojans, which are often in the form of maliciously inserted circuitry, may impact the original design by data leakage or circuit malfunction. Hardware counterfeiting and IP piracy are another two serious issues costing the US economy more than $200 billion annually. A large amount of research and experimentation has been carried out on the design of these primitives based on the currently prevailing CMOS technology. However, the security provided by these primitives comes at the cost of large overheads mostly in terms of area and power consumption. The development of emerging technologies provides hardware security researchers with opportunities to utilize some of the otherwise unusable properties of emerging technologies in security applications. In this dissertation, we will include the security consideration in the overall performance measurements to fully compare the emerging devices with CMOS technology. The first approach is to leverage two emerging devices (Silicon NanoWire and Graphene SymFET) for hardware security applications. Experimental results indicate that emerging device based solutions can provide high level circuit protection with relatively lower performance overhead compared to conventional CMOS counterpart. The second topic is to construct an energy-efficient DPA-resilient block cipher with ultra low-power Tunnel FET. Current-mode logic is adopted as a circuit-level solution to countermeasure differential power analysis attack, which is mostly used in the cryptographic system. The third investigation targets on potential security vulnerability of foundry insider\u27s attack. Split manufacturing is adopted for the protection on radio-frequency (RF) circuit design

A novel 0.6V MCML D-latch topology exploiting dynamic body bias threshold lowering

This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art. At the best of our knowledge, no other CML D-Latch topologies are able to operate at such a low supply voltage. The triple-tail D-Latch, also known as low voltage CML D-Latch allows a minimum supply voltage of 0.8V in the same reference 40nm CMOS process