A New Test Data Compression Scheme for Multi-scan Designs

In this paper we present a new test data compression scheme for multi-scan designs to reduce the test data volume and thus the test cost. The proposed method achieves the target in two steps. First a drive bit matrix with less columns is generated by exploiting the compatibilities between the columns of the initial scan bit matrix, as well as the inverse compatibilities and the logic dependencies between the columns of the mid bit matrices. Then a dictionary bit matrix with limited rows is constructed, having the properties that for each row of the drive bit matrix a compatible row exists or can be generated by an XOR operation on multiple rows in the dictionary bit matrix, and the total numbers of rows in the dictionary bit matrix used to compute all the compatible rows is minimal. The rows in the dictionary matrix are encoded to further reduce the number of ATE channels and the test data volume. The experimental results for the large ISCAS 89 benchmarks show that the proposed method significantly reduces test data volume for multi-scan designs.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000246800400028&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Computer Science, Hardware & ArchitectureEICPCI-S(ISTP)

Weighted Pseudorandom Hybrid BIST

Abstract—This paper presents a new test data-compression scheme that is a hybrid approach between external testing and built-in self-test (BIST). The proposed approach is based on weighted pseudorandom testing and uses a novel approach for compressing and storing the weight sets. Three levels of compression are used to greatly reduce test costs. Experimental results show that the proposed scheme reduces tester storage requirements and tester bandwidth requirements by orders of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. No test points or any modifications are made to the function logic. The paper describes the proposed hybrid BIST architecture as well as two different ways of storing the weight sets, which are an integral part of this scheme. I