2 research outputs found

    Efficient modular arithmetic units for low power cryptographic applications

    Get PDF
    The demand for high security in energy constrained devices such as mobiles and PDAs is growing rapidly. This leads to the need for efficient design of cryptographic algorithms which offer data integrity, authentication, non-repudiation and confidentiality of the encrypted data and communication channels. The public key cryptography is an ideal choice for data integrity, authentication and non-repudiation whereas the private key cryptography ensures the confidentiality of the data transmitted. The latter has an extremely high encryption speed but it has certain limitations which make it unsuitable for use in certain applications. Numerous public key cryptographic algorithms are available in the literature which comprise modular arithmetic modules such as modular addition, multiplication, inversion and exponentiation. Recently, numerous cryptographic algorithms have been proposed based on modular arithmetic which are scalable, do word based operations and efficient in various aspects. The modular arithmetic modules play a crucial role in the overall performance of the cryptographic processor. Hence, better results can be obtained by designing efficient arithmetic modules such as modular addition, multiplication, exponentiation and squaring. This thesis is organized into three papers, describes the efficient implementation of modular arithmetic units, application of these modules in International Data Encryption Algorithm (IDEA). Second paper describes the IDEA algorithm implementation using the existing techniques and using the proposed efficient modular units. The third paper describes the fault tolerant design of a modular unit which has online self-checking capability --Abstract, page iv

    PERFORMANCE COMPARISON REVIEW OF 8-3 COMPRESSOR ON FPGA

    Get PDF
    Compressors are commonly utilized in multipliers to cut down partial products in a parallel manner. Its main usage in this project is to go beyond the limit of fabrication technology to improve the computer performance. 2:1 compressors (half adder), 3:2 compressors (full adder), and 4:2 compressors should be well understood as it is the fundamental for building higher order compressors. In this paper, a 7-3, 8-3, 8-4, 9-3, and 9-4 researched compressors design either consisted of adder circuits or multiplexer circuits will be discussed and compared in terms of number of logic gates used, cell area and power delay product (PDP) in order to find the best method to implement the 8-3 compressor design
    corecore