System level performance and yield optimisation for analogue integrated circuits

Advances in silicon technology over the last decade have led to increased integration of analogue and digital functional blocks onto the same single chip. In such a mixed signal environment, the analogue circuits must use the same process technology as their digital neighbours. With reducing transistor sizes, the impact of process variations on analogue design has become prominent and can lead to circuit performance falling below specification and hence reducing the yield.This thesis explores the methodology and algorithms for an analogue integrated circuit automation tool that optimizes performance and yield. The trade-offs between performance and yield are analysed using a combination of an evolutionary algorithm and Monte Carlo simulation. Through the integration of yield parameter into the optimisation process, the trade off between the performance functions can be better treated that able to produce a higher yield. The results obtained from the performance and variation exploration are modelled behaviourally using a Verilog-A language. The model has been verified with transistor level simulation and a silicon prototype.For a large analogue system, the circuit is commonly broken down into its constituent sub-blocks, a process known as hierarchical design. The use of hierarchical-based design and optimisation simplifies the design task and accelerates the design flow by encouraging design reuse.A new approach for system level yield optimisation using a hierarchical-based design is proposed and developed. The approach combines Multi-Objective Bottom Up (MUBU) modelling technique to model the circuit performance and variation and Top Down Constraint Design (TDCD) technique for the complete system level design. The proposed method has been used to design a 7th order low pass filter and a charge pump phase locked loop system. The results have been verified with transistor level simulations and suggest that an accurate system level performance and yield prediction can be achieved with the proposed methodology

Design and application of reconfigurable circuits and systems

Open Acces

A power-scalable variable-length analogue DFT processor for multi-standard wireless transceivers

In the Orthogonal Frequency-Division Multiplexing (OFDM) based transceivers, digital computation of the Discrete Fourier Transform (DFT) is a power hungry process. Reduction in the hardware cost and power consumption is possible by implementing the DFT processor with analogue circuits. This thesis presents the real-time recursive DFT processor. Previously, changing the transform length and scaling the power could only be performed by digital Fast Fourier Transform (FFT) processors. By using the real-time recursive DFT processor, the decimation filter is eliminated. Thus, further reduction in the hardware cost and power consumption of the multi-standard transceiver is achieved. The real-time recursive DFT processor was designed in 180 nm CMOS technology. Results of device mismatch analysis indicate that the 8-point recursive DFT processor has a yield of 97.5% for the BPSK modulated signal. For the QPSK modulated signal, however, yield of the 8-point recursive DFT processor is 8.9%. Moreover, doubling the transform length reduces the average dynamic range by 3dB. Accordingly, the 16-point recursive DFT processor has a yield of 43.4% for the BPSK modulated signal. Power consumption of the recursive DFT processor is about 1/6 of the power consumption of a previous analogue FFT processor

Advanced avionics applications simulation platform (AAASP) for accurate aircraft systems simulation

A persistent problem for Aircraft Manufacturers has been the difficulty in carrying out accurate and robust simulations of the complete aircraft power network, while including numerous models from a variety of individual equipment suppliers. Often the models are of variable or low quality, with ill-defined parameters or behavior, and in many cases of the wrong level of abstraction to be appropriate for large scale network simulations. In addition, individual equipment suppliers often provide poor models for network integration, with a common issue being low robustness of models leading to lack of convergence, excessive simulation times and delays in development due to the need for rework and extensive testing of these models. In order to address this specific issue a complete library of power electronic system models for Aerospace applications has been developed that encompasses the range of functions from elementary components (passives, devices, switches and magnetic components), intermediate building blocks (rectifiers, inverters, motors, protection devices) and finally complete system models (variable frequency starter generators, power converters, battery and storage elements, transformers). These models have been developed in partnership with several key aircraft equipment suppliers and in partnership with Airbus to ensure that the resulting models are complete and robust. Specific equipment models were also developed in this library including permanent magnet generators, synchronous machines, environmental control systems, wing ice protection systems, power electronic modules and advanced power protection systems. The specific models have been validated against reference and measured data to ensure that they are consistent and accurate.This paper will describe the techniques used to achieve more robust models, using model based engineering, the integration of specific equipment models into the complete aircraft network and the validation of the behavior against measured results. The paper will provide the results of a complete aircraft power network highlighting how the individual models are integrated into the overall network model and the inherent robustness ensure effective, accurate and robust simulations.<br/

Symbolic tolerance and sensitivity analysis of large scale electronic circuits

Available from British Library Document Supply Centre-DSC:DXN029693 / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

An investigation into adaptive power reduction techniques for neural hardware

In light of the growing applicability of Artificial Neural Network (ANN) in the signal processing field [1] and the present thrust of the semiconductor industry towards lowpower SOCs for mobile devices [2], the power consumption of ANN hardware has become a very important implementation issue. Adaptability is a powerful and useful feature of neural networks. All current approaches for low-power ANN hardware techniques are ‘non-adaptive’ with respect to the power consumption of the network (i.e. power-reduction is not an objective of the adaptation/learning process). In the research work presented in this thesis, investigations on possible adaptive power reduction techniques have been carried out, which attempt to exploit the adaptability of neural networks in order to reduce the power consumption. Three separate approaches for such adaptive power reduction are proposed: adaptation of size, adaptation of network weights and adaptation of calculation precision. Initial case studies exhibit promising results with significantpower reduction