Synthesis of speed independent circuits based on decomposition

Journal ArticleThis paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the STG to include only transitions on the output of interest and its trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals which must be reintroduced into the STG to obtain CSC. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full state space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool nutas (Nii-Utah Timed Asynchronous circuit Synthesis system), and its very first version is available at http://research.nii.ac.jp/~yoneda. Key Words: Decomposition, synthesis, STGs, abstraction, speed-independent circuits

Synthesis of timed circuits based on decomposition

Journal ArticleAbstract-This paper presents a decomposition-based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed signal transition graph (STG) to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted STG is analyzed to determine a minimal number of additional signals, which must be reintroduced into the STG to obtain complete state coding. The circuit for this output is then synthesized from this STG. Results show that the quality of the circuit implementation is nearly as good as the one found from the full reachable state space, but it can be applied to find circuits for which full-state-space methods cannot be successfully applied. The proposed method has been implemented as a part of our tool Nii-Utah Timed Asynchronous circuit Synthesis system (nutas), and its first version is available at http://research.nii.ac.jp/~yoneda

Integration of constraint programming and linear programming techniques for constraint satisfaction problem and general constrained optimization problem.

Wong Siu Ham.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 131-138).Abstracts in English and Chinese.Abstract --- p.iiAcknowledgments --- p.viChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation for Integration --- p.2Chapter 1.2 --- Thesis Overview --- p.4Chapter 2 --- Preliminaries --- p.5Chapter 2.1 --- Constraint Programming --- p.5Chapter 2.1.1 --- Constraint Satisfaction Problems (CSP's) --- p.6Chapter 2.1.2 --- Satisfiability (SAT) Problems --- p.10Chapter 2.1.3 --- Systematic Search --- p.11Chapter 2.1.4 --- Local Search --- p.13Chapter 2.2 --- Linear Programming --- p.17Chapter 2.2.1 --- Linear Programming Problems --- p.17Chapter 2.2.2 --- Simplex Method --- p.19Chapter 2.2.3 --- Mixed Integer Programming Problems --- p.27Chapter 3 --- Integration of Constraint Programming and Linear Program- ming --- p.29Chapter 3.1 --- Problem Definition --- p.29Chapter 3.2 --- Related works --- p.30Chapter 3.2.1 --- Illustrating the Performances --- p.30Chapter 3.2.2 --- Improving the Searching --- p.33Chapter 3.2.3 --- Improving the representation --- p.36Chapter 4 --- A Scheme of Integration for Solving Constraint Satisfaction Prob- lem --- p.37Chapter 4.1 --- Integrated Algorithm --- p.38Chapter 4.1.1 --- Overview of the Integrated Solver --- p.38Chapter 4.1.2 --- The LP Engine --- p.44Chapter 4.1.3 --- The CP Solver --- p.45Chapter 4.1.4 --- Proof of Soundness and Completeness --- p.46Chapter 4.1.5 --- Compared with Previous Work --- p.46Chapter 4.2 --- Benchmarking Results --- p.48Chapter 4.2.1 --- Comparison with CLP solvers --- p.48Chapter 4.2.2 --- Magic Squares --- p.51Chapter 4.2.3 --- Random CSP's --- p.52Chapter 5 --- A Scheme of Integration for Solving General Constrained Opti- mization Problem --- p.68Chapter 5.1 --- Integrated Optimization Algorithm --- p.69Chapter 5.1.1 --- Overview of the Integrated Optimizer --- p.69Chapter 5.1.2 --- The CP Solver --- p.74Chapter 5.1.3 --- The LP Engine --- p.75Chapter 5.1.4 --- Proof of the Optimization --- p.77Chapter 5.2 --- Benchmarking Results --- p.77Chapter 5.2.1 --- Weighted Magic Square --- p.77Chapter 5.2.2 --- Template design problem --- p.78Chapter 5.2.3 --- Random GCOP's --- p.79Chapter 6 --- Conclusions and Future Work --- p.97Chapter 6.1 --- Conclusions --- p.97Chapter 6.2 --- Future work --- p.98Chapter 6.2.1 --- Detection of implicit equalities --- p.98Chapter 6.2.2 --- Dynamical variable selection --- p.99Chapter 6.2.3 --- Analysis on help of linear constraints --- p.99Chapter 6.2.4 --- Local Search and Linear Programming --- p.99Appendix --- p.101Proof of Soundness and Completeness --- p.101Proof of the optimization --- p.126Bibliography --- p.13

A modular partitioning approach for asynchronous circuit synthesis

Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous circuits is a difficult and error-prone task. An adequate synthesis method will significantly simplify the design and reduce errors. In this paper, we present a general and efficient partitioning approach to the synthesis of asynchronous circuits from general Signal Transition Graph (STG) specifications. The method partitions a large signal transition graph into smaller and manageable subgraphs which significantly reduces the complexity of asynchronous circuit synthesis. Experimental results of our partitioning approach with large number of practical industrial asynchronous circuit benchmarks are presented. They show that, compared to the existing asynchronous circuit synthesis techniques, this partitioning approach achieves many orders of magnitude of performance improvements in terms of computing time, in addition to the reduced circuit implementation area. This lends itself well to practical asynchronous circuit synthesis from general STG specifications