High Peformance and Low Power On-Die Interconnect Fabrics.

Increasing power density with technology scaling has caused stagnation in operating frequency of modern day microprocessors. This has led designers to prefer multicore architectures over complex monolithic processors to keep up with the demand for rising computing throughput. Although processing units are getting smaller and simpler, the dramatic rise of their count on a single die has made the fabric that connects these processing units increasingly complex. These interconnect fabrics have become a bottleneck in improving overall system effciency. As a result, the design paradigm for multi-core chips is gradually shifting from a core-centric architecture towards an interconnect-centric architecture, where system efficiency is limited by the fabric rather than the processing ability of any individual core. This dissertation introduces three novel and synergistic circuit techniques to improve scalability of switch fabrics to make on-die integration of hundreds to thousands of cores feasible. 1) A matrix topology is proposed for designing a fully connected switch fabric that re-uses output buses for programming, and stores shue congurations at cross points. This significantly reduces routing congestion, lowers area/power, and improves per- formance. Silicon measurements demonstrate 47% energy savings in a 64-lane SIMD processor fabricated in 65nm CMOS over a conventional implementation. 2) A novel approach to handle high radix arbitration along with data routing is proposed. It optimally uses existing cross-bar interconnect resources without requiring any additional overhead. Bandwidth exceeding 2Tb/s is recorded in a test prototype fabricated in 65nm. 3) Building on the later, a new circuit topology to manage and update priority adaptively within the switch fabric without incurring additional delay or area is then proposed. Several assist circuit techniques, such as a thyristor based sense amplifier and self regenerating bi-directional repeaters are proposed for high speed energy efficient signaling to and from the switch fabric to improve overall routing efficiency. Using these techniques a 64 x 64 switch fabric with 128b data bus fabricated in 45nm achieves a throughput of 4.5Tb/s at single cycle latency while operating at 559MHz.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91506/1/sudhirks_1.pd

Comparison of SOI, power device structures in power converters for high-voltage, low-charge electrostatic microgenerators

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A Physical Implementation with Custom Low Power Extensions of a Reconfigurable Hardware Fabric

The primary focus of this thesis is on the physical implementation of the SuperCISC Reconfigurable Hardware Fabric (RHF). The SuperCISC RHF provides a fast time to market solution that approximates the benefits of an ASIC (Application Specific Integrated Circuit) while retaining the design flow of an embedded software system. The fabric which consists of computational ALU stripes and configurable multiplexer based interconnect stripes has been implemented in the IBM 0.13um CMOS process using Cadence SoC Encounter. As the entire hardware fabric utilizes a combinational flow, glitching power consumption is a potential problem inherent to the fabric. A CMOS thyristor based programmable delay element has been designed in the IBM 0.13um CMOS process, to minimize the glitch power consumed in the hardware fabric. The delay element was characterized for use in the IBM standard cell library to synthesize standard cell ASIC designs requiring this capability such as the SuperCISC fabric. The thesis also introduces a power-gated memory solution, which can be used to increase the size of an EEPROM memory for use in SoC style applications. A macromodel of the EEPROM has been used to model the erase, program and read characteristics of the EEPROM. This memory is designed for use in the fabric for storing encryption keys, etc

Low-Leakage ESD Power Supply Clamps in General Purpose 65 nm CMOS Technology

Electrostatic discharge (ESD) is a well-known contributor that reduces the reliability and yield of the integrated circuits (ICs). As ICs become more complex, they are increasingly susceptible to such failures due to the scaling of physical dimensions of devices and interconnect on a chip [1]. These failures are caused by excessive electric field and/or excessive current densities and result in the dielectric breakdown, electromigration of metal lines and contacts. ESD can affect the IC in its different life stages, from wafer fabrication process to failure in the field. Furthermore, ESD events can damage the integrated circuit permanently (hard failure), or cause a latent damage (soft failure) [2]. ESD protection circuits consisting of I/O protection and ESD power supply clamps are routinely used in ICs to protect them against ESD damage. The main objective of the ESD protection circuit is to provide a low-resistive discharge path between any two pins of the chip to harmlessly discharge ESD energy without damaging the sensitive circuits. The main target of this thesis is to design ESD power supply clamps that have the lowest possible leakage current without degrading the ESD protection ability in general purpose TSMC 65 nm CMOS technology. ESD clamps should have a very low-leakage current and should be stable and immune to the power supply noise under the normal operating conditions of the circuit core. Also, the ESD clamps must be able to handle high currents under an ESD event. All designs published in the general purpose 65 nm CMOS technology have used the SCR as the clamping element since the SCR has a higher current carrying capability compared to an MOS transistor of the same area [3]. The ESD power supply clamp should provide a low-resistive path in both directions to be able to deal with both PSD and NDS zapping modes. The SCR based design does not provide the best ESD protection for the NDS zapping mode (positive ESD stress at VSS with grounded VDD node) since it has two parasitic resistances (RNwell and RPsub) and one parasitic diode (the collector to base junction diode of the PNP transistor) in the path from the VSS to VDD. Furthermore, SCR-based designs are not suitable for application that exposed to hot switching or ionizing radiation [2]. In GP process, the gate oxide thickness of core transistors is reduced compared with LP process counterpart to achieve higher performance designs for high-frequency applications using 1 V core transistors and 2.5 V I/O option. The thinner gate oxide layer results in higher leakage current due to gate tunneling [4]. Therefore, using large thin oxide MOS transistors as clamping elements will result in a huge leakage. In this thesis, four power supply ESD clamps are proposed in which thick oxide MOS transistors are used as the main clamping element. Therefore, the low-leakage current feature is achieved without significantly degrading the ESD performance. In addition, the parasitic diode of the MOS transistors provides the protection against NSD-mode. In this thesis, two different ESD power supply clamp architectures are proposed: standalone ESD power supply clamps and hybrid ESD power supply clamps. Two standalone clamps are proposed: a transient PMOS based ESD clamp with thyristor delay element (PTC), and a static diode triggered power supply (DTC). The standalone clamps were designed to protect the circuit core against ±125 V CDM stress by limiting the voltage between the two power rails to less than the oxide breakdown voltage of the core transistors, BVOXESD = 5 V. The large area of this architecture was the price for maintaining the low-leakage current and an adequate ESD protection. The hybrid clamp architecture was proposed to provide a higher ESD protection, against ±300 V CDM stress, while reducing the layout area and maintaining the low-leakage feature. In the hybrid clamp structure, two clamps are connected in parallel between the two power supply rails, a static clamp, and a transient clamp. The static clamp triggers first and starts to sink the ESD energy and then an RC network triggers the primary transient clamp to sink most of the ESD stress. Two hybrid designs were proposed: PMOS ESD power supply clamp with thyristor delay element and diodes (PTDC), and NMOS ESD power supply clamp with level shifter delay element and diode (NLDC). Simulation results show that the proposed clamps are capable of protecting the circuit core against ±1.5 kV HBM and at least against ±125 V CDM stresses. The measurement results show that all of the proposed clamps are immune against false triggering, and transient induced latch-up. Furthermore, all four designs have responded favorably to the 4 V ESD-like pulse voltage under both chip powered and not powered conditions and after the stress ends the designs turned off. Finally, TLP measurement results show that all four proposed designs meet the minimum design requirement of the ESD protection circuit in the 65 nm CMOS technology (i.e. HBM protection level of ±1.5 kV )

Electrostatic discharge protection circuit for high-speed mixed-signal circuits

ESD, the discharge of electrostatically generated charges into an IC, is one of the most important reliability problems for ultra-scaled devices. This electrostatic charge can generate voltages of up to tens of kilovolts. These very high voltages can generate very high electric fields and currents across semiconductor devices, which may result in dielectric damage or melting of semiconductors and contacts. It has been reported that up to 70% of IC failures are caused by ESD. Therefore, it’s necessary to design a protection circuit for each pin that discharges the ESD energy to the ground. As the devices are continuously scaling down, while ESD energy remains the same, they become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Providing a complete ESD immunity for any circuit involves the design of proper protection circuits for I/O pins in addition to an ESD clamp between power supply pins. In this research both of these aspects are investigated and optimized solutions for them are reported. As Silicon Controlled Rectifier (SCR) has the highest ESD protection level per unit area, ESD protection for I/O pins is provided by optimizing the first breakdown voltage and latch-up immunity of SCR family devices. The triggering voltage of SCR is reduced by a new implementation of gate-substrate triggering technique. Furthermore, a new device based on SCR with internal darlington pair is introduced that can provide ESD protection with very small parasitic capacitance. Besides reducing triggering voltage, latch-up immunity of SCR devices is improved using two novel techniques to increase the holding voltage and the holding current. ESD protection between power rails is provided with transient clamps in which the triggering circuit keeps the clamp “on” during the ESD event. In this research, two new clamps are reported that enhance the triggering circuit of the clamp. The first method uses a CMOS thyristor element to provide enough delay time while the second method uses a flip flop to latch the clamp into “on” state at the ESD event. Moreover, the stability of transient clamps is analyzed and it’s been shown that the two proposed clamps have the highest stability compared to other state of the art ESD clamps. Finally, in order to investigate the impact of ESD protection circuits on high speed applications a current mode logic (CML) driver is designed in 0.13μm CMOS technology. The protection for this driver is provided using both MOS-based and SCR-based protection methods. Measurement results show that, compared to MOS-based protection, SCR-based protection has less impact on the driver performance due to its lower parasitic capacitance

RF Power Transfer, Energy Harvesting, and Power Management Strategies

Energy harvesting is the way to capture green energy. This can be thought of as a recycling process where energy is converted from one form (here, non-electrical) to another (here, electrical). This is done on the large energy scale as well as low energy scale. The former can enable sustainable operation of facilities, while the latter can have a significant impact on the problems of energy constrained portable applications. Different energy sources can be complementary to one another and combining multiple-source is of great importance. In particular, RF energy harvesting is a natural choice for the portable applications. There are many advantages, such as cordless operation and light-weight. Moreover, the needed infra-structure can possibly be incorporated with wearable and portable devices. RF energy harvesting is an enabling key player for Internet of Things technology. The RF energy harvesting systems consist of external antennas, LC matching networks, RF rectifiers for ac to dc conversion, and sometimes power management. Moreover, combining different energy harvesting sources is essential for robustness and sustainability. Wireless power transfer has recently been applied for battery charging of portable devices. This charging process impacts the daily experience of every human who uses electronic applications. Instead of having many types of cumbersome cords and many different standards while the users are responsible to connect periodically to ac outlets, the new approach is to have the transmitters ready in the near region and can transfer power wirelessly to the devices whenever needed. Wireless power transfer consists of a dc to ac conversion transmitter, coupled inductors between transmitter and receiver, and an ac to dc conversion receiver. Alternative far field operation is still tested for health issues. So, the focus in this study is on near field. The goals of this study are to investigate the possibilities of RF energy harvesting from various sources in the far field, dc energy combining, wireless power transfer in the near field, the underlying power management strategies, and the integration on silicon. This integration is the ultimate goal for cheap solutions to enable the technology for broader use. All systems were designed, implemented and tested to demonstrate proof-of concept prototypes

Ultra-low Power Circuits for Internet of Things (IOT)

Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT. In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible. Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy. Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd

An Integrated BiCMOS driver chip for medium power applications

The development of an integrated driver circuit intended for medium power switching applications is presented. The device contains, on one chip, CMOS digital control logic and bipolar drivers, with BiCMOS interface between the two technologies. The custom integrated circuit includes four outputs each capable of switching over 500 mA at 30 volts, at a frequency of up to 1 MHz. The development effort includes the design of the chip with its component circuits and cells. Standard cell CMOS logic gates along with drive and interface circuits were designed and characterized. An appropriate BiCMOS process was developed which utilizes an n-well based 4-micron polysilicon gate MOS technology and vertical NPNs with subcollector and double emitter implants. The chip performance specifications are evaluated with respect to technology requirements and device characteristics, and trade-offs in the design of the chip and the process are examined. Process and device modeling results are compared with the measured data, which show that the objectives of the design are successfully met for the various applications involving resistive, capacitive, and inductive loads