Dual-frequency single-inductor multiple-output (DF-SIMO) power converter topology for SoC applications

Modern mixed-signal SoCs integrate a large number of sub-systems in a single nanometer CMOS chip. Each sub-system typically requires its own independent and well-isolated power supply. However, to build these power supplies requires many large off-chip passive components, and thus the bill of material, the package pin count, and the printed circuit board area and complexity increase dramatically, leading to higher overall cost. Conventional (single-frequency) Single-Inductor Multiple-Output (SIMO) power converter topology can be employed to reduce the burden of off-chip inductors while producing a large number of outputs. However, this strategy requires even larger off-chip output capacitors than single-output converters due to time multiplexing between the multiple outputs, and thus many of them suffer from cross coupling issues that limit the isolation between the outputs. In this thesis, a Dual-Frequency SIMO (DF-SIMO) buck converter topology is proposed. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency (~2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A 5-output 2-MHz/120-MHz design in 45-nm CMOS with 1.8-V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10-uH off-chip inductor, 2-nF on-chip capacitor for each 15-mA output and 4.5-nF for the 50-mA output. The peak efficiency is 73%, Dynamic Voltage Scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-coupling transients. The DF-SIMO topology enables realizing multiple efficient power supplies with faster dynamic response, better cross-regulation, and lower overall cost compared to conventional SIMO topologies

Dual-frequency dual-inductor multiple-outputs (DF-DIMO) buck converter topologies with fully-integrated output filters

In multi-core DSPs, there is a need for multiple independent power supplies to power the digital cores. Each power supply needs to have fast dynamic response and must support a wide range of output voltage with up to hundreds of mA load current. In this dissertation, the key performance metrics in power converter design are introduced, the advantages and dis-advantages of the conventional power converter topology are analyzed and a new Dual-Frequency Dual-Inductor Multiple-Output (DF-DIMO) buck converter topology is presented to improve the limitations of the conventional topologies. The proposed topology employs a dual-phase 20-MHz current-mode-controlled input stage to reduce the inductance required per phase to only 200 nH, and a 4-output 100-MHz comparator-controlled fully-integrated output stage to reduce the capacitance required per output to 10 nF. To enable each output to handle up to 250-mA load with less than 40-mV voltage ripple, a 3rd-order bond-wire-based notch filter is employed at each output for voltage ripple suppression. Additionally, the proposed design employs dynamic output re-ordering to enhance dynamic and cross-regulation performance, interleaved pulse-skipping to enhance light-load efficiency, and high-gain local output feedback to enhance DC load Regulation. Targeting multi-core DSPs, the proposed design is implemented in standard 65-nm CMOS technology with 1.8-V input, and outputs in the range of 0.6–1.2 V with a total load of 1 A. It achieves a peak efficiency of 74%, less than 40-mV output voltage ripple, 0.5-V/70-ns Dynamic Voltage Scaling (DVS), and settling time of less than 85 ns for 125-mA all with no cross regulations

Power conversion techniques in nanometer CMOS for low-power applications

As System-on-Chip (SoCs) in nanometer CMOS technologies grow larger, the power management process within these SoCs becomes very challenging. In the heart of this process lies the challenge of implementing energy-efficient and cost-effective DC-DC power converters. To address this challenge, this thesis studies in details three different aspects of DC-DC power converters and proposes potential solutions. First, to maximize power conversion efficiency, loss mechanisms must be studied and quantified. For that purpose, we provide comprehensive analysis and modeling of the various switching and conduction losses in low-power synchronous DC-DC buck converters in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM) operation, including the case with non-rail gate control of the power switches. Second, a DC-DC buck converter design with only on-chip passives is proposed and implemented in 65-nm CMOS technology. The converter switches at 588 MHz and uses a 20-nH and 300-pF on-chip inductor and capacitor respectively, and provides up to 30-mA of load at an output voltage in the range of 0.8-1.2 V. The proposed design features over 10% improvement in power conversion efficiency over a corresponding linear regulator while preserving low-cost implementation. Finally, a 40-mA buck converter design operating in the inherently-stable DCM mode for the entire load range is presented. It employs a Pulse Frequency Modulation (PFM) scheme using a Hysteretic-Assisted Adaptive Minimum On-Time (HA-AMOT) controller to automatically adapt to a wide range of operating scenarios while minimizing inductor peak current. As a result, compact silicon area, low quiescent current, high efficiency, and robust performance across all conditions can be achieved without any calibration

Power management using photovoltaic cells for implantable devices

This paper presents a novel inductor-less switched capacitor (SC) DC-DC converter, which generates simultaneous dual-output voltages for implantable electronic devices. Present dual output converters are limited to fixed ratio gain, which degrade conversion efficiency when the input voltage changes. The proposed power converter offers both step-up and step-down conversion with 4-phase reconfigurable logic. With an input voltage of 1 V provided by photovoltaic (PV) cells, the proposed converter achieves step-up, step-down and synchronised voltage conversions in four gain modes. These are 1.5 V and 0.5 V for Normal mode, 2 V and 1 V for High mode, 2 V for Double Boost mode, as well as 3 V and 2 V for Super Boost mode with the ripple variation of 14-59 mV. The converter circuit has been simulated in standard 0.18 μm CMOS technology and the results agree with state-of-the-art SC converters. However, our proposed monolithically integrated PV powered circuit achieves a conversion efficiency of 85.26% and provides extra flexibility in terms of gain, which is advantageous for future implantable applications that have a range of inputs. This research is therefore an important step in achieving truly autonomous implantable electronic devices

Battery-sourced switched-inductor multiple-output CMOS power-supply systems

Wireless microsystems add intelligence to larger systems by sensing, processing and transmitting information which can ultimately save energy and resources. Each function has their own power profile and supply level to maximize performance and save energy since they are powered by a small battery. Also, due to its small size, the battery has limited energy and therefore the power-supply system cannot consume much power. Switched-inductor converters are efficient across wide operating conditions but one fundamental challenge is integration because miniaturized dc-dc converters cannot afford to accommodate more than one off-chip power inductor. The objective of this research is to explore, develop, analyze, prototype, test, and evaluate how one switched inductor can derive power from a small battery to supply, regulate, and respond to several independent outputs reliably and accurately. Managing and stabilizing the feedback loops that supply several outputs at different voltages under diverse and dynamic loading conditions with one CMOS chip and one inductor is also challenging. Plus, since a single inductor cannot supply all outputs at once, steady-state ripples and load dumps produce cross-regulation effects that are difficult to manage and suppress. Additionally, as the battery depletes the power-supply system must be able to regulate both buck and boost voltages. The presented system can efficiently generate buck and boost voltages with the fastest response time while having a low silicon area consumption per output in a low-cost technology which can reduce the overall size and cost of the system.Ph.D

Power management systems based on switched-capacitor DC-DC converter for low-power wearable applications

The highly efficient ultra-low-power management unit is essential in powering low-power wearable electronics. Such devices are powered by a single input source, either by a battery or with the help of a renewable energy source. Thus, there is a demand for an energy conversion unit, in this case, a DC-DC converter, which can perform either step-up or step-down conversions to provide the required voltage at the load. Energy scavenging with a boost converter is an intriguing choice since it removes the necessity of bulky batteries and considerably extends the battery life. Wearable devices are typically powered by a monolithic battery. The commonly available battery such as Alkaline or Lithium-ion, degrade over time due to their life spans as it is limited by the number of charge cycles- which depend highly on the environmental and loading condition. Thus, once it reaches the maximum number of life cycles, the battery needs to be replaced. The operation of the wearable devices is limited by usable duration, which depends on the energy density of the battery. Once the stored energy is depleted, the operation of wearable devices is also affected, and hence it needs to be recharged. The energy harvesters- which gather the available energy from the surroundings, however, have no limitation on operating life. The application can become battery-less given that harvestable energy is sufficiently powering the low-power devices. Although the energy harvester may not completely replace the battery source, it ensures the maximum duration of use and assists to become autonomous and self-sustain devices. The photovoltaic (PV) cell is a promising candidate as a hypothetical input supply source among the energy harvesters due to its smaller area and high power density over other harvesters. Solar energy use PV harvester can convert ambient light energy into electrical energy and keep it in the storage device. The harvested output of PV cannot directly connect to wearable loads for two main reasons. Depending on the incoming light, the harvested current result in varying open-circuit voltage. It requires the power management circuit to deal with unregulated input variation. Second, depending on the PV cell's material type and an effective area, the I-V characteristic's performance varies, resulting in a variation of the output power. There are several works of maximum power point tracking (MPPT) methods that allow the solar energy harvester to achieve optimal harvested power. Therefore, the harvested power depends on the size and usually small area cell is sufficient for micro-watt loads low-powered applications. The available harvested voltage, however, is generally very low-voltage range between 0.4-0.6 V. The voltage ratings of electronics in standard wearable applications operate in 1.8-3 V voltages as described in introduction’s application example section. It is higher than the supply source can offer. The overcome the mismatch voltage between source and supply circuit, a DC-DC boost converter is necessary. The switch-mode converters are favoured over the linear converters due to their highly efficient and small area overhead. The inductive converter in the switch-mode converter is common due to its high-efficiency performance. However, the integration of the inductor in the miniaturised integrated on-chip design tends to be bulky. Therefore, the switched-capacitor approach DC-DC converters will be explored in this research. In the switched-capacitor converter universe, there is plenty of work for single-output designs for various topologies. Most converters are reconfigurable to the different DC voltage levels apart from Dickson and cross-coupled charge pump topologies due to their boosting power stage architecture through a number of stages. However, existing multi-output converters are limited to the fixed gain ratio. This work explores the reconfigurable dual-output converter with adjustable gain to compromise the research gap. The thesis's primary focus is to present the inductor-less, switched-capacitor-based DC-DC converter power management system (PMS) supplied by a varying input of PV energy harvester input source. The PMS should deliver highly efficient regulated voltage conversion ratio (VCR) outputs to low-power wearable electronic devices that constitute multi-function building blocks

An Analysis of Non-Isolated DC-DC Converter Topologies with Energy Transfer Media

As miniaturized mobile devices with various functionalities are highly desired, the current requirement for loading blocks is gradually increasing. Accordingly, the efficiency of the power converter that supports the current to the loading bocks is a critical specification to prolong the battery time. Unfortunately, when using a small inductor for the miniaturization of mobile devices, the efficiency of the power converter is limited due to a large parasitic DC resistance (R-DCR) of the inductor. To achieve high power efficiency, this paper proposes an energy transfer media (ETM) that can make a switched inductor capacitor (SIC) converter easier to design, maintaining the advantages of both a conventional switched capacitor (SC) converter and a switched inductive (SI) converter. This paper shows various examples of SIC converters as buck, boost, and buck-boost topologies by simply cascading the ETM with conventional non-isolated converter topologies without requiring a sophisticated controller. The topologies with the ETM offer a major advantage compared to the conventional topologies by reducing the inductor current, resulting in low conduction loss dissipated at R-DCR. Additionally, the proposed topologies have a secondary benefit of a small output voltage ripple owing to the continuous current delivered to the load. Extensions to a multi-phase converter and single-inductor multiple-output converter are also discussed. Furthermore, a detailed theoretical analysis of the total conduction loss and the inductor current reduction is presented. Finally, the proposed topologies were simulated in PSIM, and the simulation results are discussed and compared with conventional non-isolated converter topologies

Efficient power management circuits for energy harvesting applications

Low power IoT devices are growing in numbers and by 2020 there will be more than 25 Billion of those in areas such as wearables, smart homes, remote surveillance, transportation and industrial systems, including many others. Many IoT electronics either will operate from stand-alone energy supply (e.g., battery) or be self-powered by harvesting from ambient energy sources or have both options. Harvesting sustainable energy from ambient environment plays significant role in extending the operation lifetime of these devices and hence, lower the maintenance cost of the system, which in turn help make them integral to simpler systems. Both for battery-powered and harvesting capable systems, efficient power delivery unit remains an essential component for maximizing energy efficiency. The goal of this research is to investigate the challenges of energy delivery for low power electronics considering both energy harvesting as well as battery-powered conditions and to address those challenges. Different challenges of energy harvesting from low voltage energy sources based on the limitations of the sources, the type of the regulator used and the pattern of the load demands have been investigated. Different aspects of the each challenges are further investigated to seek optimized solutions for both load specific and generalized applications. A voltage boost mechanism is chosen as the primary mechanism to investigate and to addressing those challenges, befitting the need for low power applications which often rely on battery voltage or on low voltage energy harvesting sources. Additionally, a multiple output buck regulator is also discussed. The challenges analyzed include very low voltage start up issues for an inductive boost regulator, cascading of boost regulator stages, and reduction of the number of external component through reusing those. Design techniques for very high conversion ratio, bias current reduction with autonomous bias gating, battery-less cold start, component and power stage multiplexing for reconfigurable and multi-domain regulators are presented. Measurement results from several silicon prototypes are also presented.Ph.D

Modeling and Design of High-Performance DC-DC Converters

The goal of the research that was pursued during this PhD is to eventually facilitate the development of high-performance, fast-switching DC-DC converters. High-switching frequency in switching mode power supplies (SMPS) can be exploited by reducing the output voltage ripple for the same size of passives (mainly inductors and capacitors) and improve overall system performance by providing a voltage supply with less unwanted harmonics to the subsystems that they support. The opposite side of the trade-off is also attractive for designers as the same amount of ripple can be achieved with smaller values of inductance and/or capacitance which can result in a physically smaller and potentially cheaper end product. Another benefit is that the spectrum of the resulting switching noise is shifted to higher frequencies which in turn allows designers to push the corner frequency of the control loop of the system higher without the switching noise affecting the behavior of the system. This in turn, is translated to a system capable of responding faster to strong transients that are common in modern systems that may contain microprocessors or other electronics that tend to consume power in bursts and may even require the use of features like dynamic voltage scaling to minimize the overall consumption of the system. While the analysis of the open loop behavior of a DC-DC converter is relatively straightforward, it is of limited usefulness as they almost always operate in closed loop and therefore can suffer from degraded stability. Therefore, it is important to have a way to simulate their closed loop behavior in the most efficient manner possible. The first chapter is dedicated to a library of technology-agnostic high-level models that can be used to improve the efficiency of transient simulations without sacrificing the ability to model and localize the different losses. This work also focuses further in fixed-frequency converters that employ Peak Current Mode Control (PCM) schemes. PCM schemes are frequently used due to their simple implementation and their ability to respond quickly to line transients since any change of the battery voltage is reflected in the slope of the rising inductor current which in turn is monitored by a fast internal control loop that is closed with the help of a current sensor. Most existing models for current sensors assume that they behave in an ideal manner with infinite bandwidth and ideal constant gain. These assumptions tend to be in significant error as the minimum on-time of the sensor and therefore the settling time requirements of the sensor are reduced. Some sensing architectures, like the ones that approximate the inductor current with the high-side switch current, can be even more complex to analyze as they require the use of extended masking time to prevent spike currents caused by the switch commutation to be injected to the output of the sensor and therefore the signal processing blocks of the control loop. In order to solve this issue, this work also proposes a current sensor model that is compatible with time averaged models of DC-DC converters and is able to predict the effects of static and transient non-idealities of the block on the behavior of a PCM DC-DC converter. Lastly, this work proposes a new 40 V, 6 A, fully-integrated, high-side current sensing circuit with a response time of 51 . The proposed sensor is able to achieve this performance with the help of a feedback resistance emulation technique that prevents the sensor from debiasing during its masking phase which tends to extend the response time of similar fully integrated sensors

WIRELESS POWER MANAGEMENT CIRCUITS FOR BIOMEDICAL IMPLANTABLE SYSTEMS

Ph.DDOCTOR OF PHILOSOPH