Modular architecture for ultra low power switched-capacitor DC-DC converters

This work presents a novel architecture for a step down Switched Capacitor Converter for Ultra Low Power applications such as implantable devices,Wireless Sensor Nodes, portable devices, etc. The objective is to supply energy to digital circuits such as micro-controllers using the Dynamic Voltage Scaling technique that allows to optimize the trade-off between performance and consumption. Other important applications of this type of converters are the newest technologies where the transistors are not able to tolerate the voltage provided by the different types of batteries. The more conversion ratios the converter has the better to apply the Dynamic Voltage Scaling technique it is. This is because different performance levels in digital circuits need different supply voltages to minimize the power consumption while achieving the needed performance. In the literature there are some works in the area, all of them with the particularity of having a rigid architecture based on particular configurations for each conversion level. This makes this type of converters not suitable for adding easily more conversion ratios. The architecture proposed in this work has the particularity of being modular and being able to easily add new conversion ratios if necessary. Each module (named Basic Capacitor Cell) is composed by a capacitor and a fourswitch configuration. The number of modules used in the converter defines the number of conversion ratios. The Basic Capacitor Cells are connected in a ring configuration that can be opened in each node to connect the supply voltage. Then the load is connected to one of the intermediate nodes. Given the modularity of the converter a general numerical model was developed. This model allows to predict the performance of the converter for an arbitrary number of conversion ratios. As the model uses some data extracted from electrical simulation and some parameters of the technology, it can easily be used for any technology. The model is suitable to make design space exploration and avoid long electrical simulations times. A four-conversion-ratios converter was developed and electrically simulated in the technology On Semi 0,5μm with an input voltage of 2,8V . The peak efficiency achieved is 78%. This performance is similar to the one achieved by existing works in the literature. The logic was implemented but not the control loop. A novel technique to improve the losses in parasitic capacitances was proposed and simulated. This technique makes a redistribution of the charge between the parasitic capacitances that need to lose energy and those that need to gain energy. Since parasitic capacitances losses are dominant in this architecture.Este trabajo presenta una arquitectura novedosa para la implementacion de convertidores DC-DC de condensadores conmutados de Ultra Bajo Consumo para aplicaciones como dispositivos implantables, redes de sensores inalambricos, dispositivos portatiles, entre otros. El objetivo es suministrar energia a circuitos digitales tales como microcontroladores usando la tecnica de escalado dinamico de voltaje que permite manejar el compromiso entre la performance y el consumo del circuito. Otra importante aplicacion de este tipo de convertidores es para las nuevas tecnologias donde los transistores no soportan el voltaje entregado por los distintos tipos de pilas. Cuantos mas niveles de conversion tenga el convertidor mejor se puede aplicar la tecnica de escalado dinamico de voltaje. Esto es porque diferentes niveles de performance de un circuito digital necesitan diferentes voltajes de alimentacion para minimizar la potencia disipada alcanzando la performance necesaria. Existen algunos trabajos en el area, todos ellos tienen la particularidad de utilizar arquitecturas rigidas basadas en configuraciones particulares para cada nivel de conversion. Esto hace que este tipo de convertidores no sea apropiado para aumentar facilmente la cantidad de niveles de conversion. La arquitectura propuesta en este trabajo tiene la particularidad de ser modular y permite facilmente agregar mas niveles de conversion si fuera necesario, a la vez que simplifica el dise?ada modulo esta compuesto por un condensador y una configuracion de cuatro switches. El numero de modulos usado en el convertidor define el numero de niveles de conversion. Los modulos son conectados en forma de anillo el cual puede ser abierto en cualquiera de los nodos con el fin de conectar la fuente de alimentacion. Luego la carga es conectada a uno de los nodos intermedios del anillo segun el nivel de conversion deseado. Dada la modularidad del convertidor un modelo numerico general fue desarrollado. Este modelo permite tener una prediccion de la performance del convertidor para un numero arbitrario de niveles de conversion. Dado que el modelo utiliza datos extraidos de simulaciones electricas y algunos parametros de la tecnologia, facilmente puede ser usado para cualquier tecnologia. El modelo es apropiado para realizar exploraciones del espacio de dise? evitar los prolongados tiempos de las simulaciones electricas. Un convertidor de cuatro niveles de conversion fue desarrollado y simulado a nivel electrico en la tecnologia On Semi 0,5µm con un voltaje de alimentacion de 2,8V . El pico de eficiencia alcanzado es de 78%. Esta performance es similar a la alcanzada por los trabajos existentes en la literatura. Para este convertidor la logica fue implementado, pero no el lazo de control que fija la tension de salida. Una novedosa tecnica para disminuir las perdidas en las capacidades parasitas fue propuesta y simulada. Dicha tecnica realiza una redistribucion de la carga entre las capacidades parasitas que necesitan perder energia y aquellas que necesitan ganarla. Dado que las perdidas en las capacidades parasitas son dominantes en esta arquitectura, una mejora significativa fue lograda en la eficiencia a partir de la aplicacion de esta tecnica

Design and Implementation of Integrated High Efficiency Low-voltage CMOS DC-DC Converters

RÉSUMÉ De nos jours, les appareils portatifs sont utilisés dans plusieurs applications. Ils utilisent en général une batterie qui doit être remplacée ou rechargée régulièrement. Dans le cas d'applications biomédicales, la durée de vie de la batterie est un paramètre critique. Pour un appareil implantable, une longue durée de vie est un objectif primordial. Cet objectif est généralement atteint en réduisant la consommation de puissance des circuits constituant l'implant. Parmi les diverses techniques existantes qui permettent la réduction de la consommation en puissance des circuits CMOS, on retrouve la technique d'ajustement dynamique de la tension (dynamic voltage scaling - DVS). En réduisant la tension d'alimentation, la consommation totale des circuits peut être diminuée. Cependant cette technique ne peut être implémentée sans faire appel à des circuits dédiés à une gestion intelligente de l'énergie. Dans ce contexte, l'utilisation de convertisseurs de tension DC-DC devient nécessaire pour économiser la charge de la batterie. Mais pour garantir une réduction effective de la consommation globale, des convertisseurs DC-DC de haute efficacité doivent être utilisés. A cette contrainte se rajoute la miniaturisation en utilisant des circuits hautement intégrés pour les applications telles que les implants biomédicaux. Le défi réside dans la conception d'un convertisseur DC-DC totalement intégré tout en assurant une haute efficacité sur une grande plage de tension de sortie. De plus, les appareils tels que les implants électroniques fonctionnent souvent en mode de veille pour réduire la consommation, entrainant ainsi des variations conséquentes de la charge du convertisseur DC-DC. Ceci rajoute un défi supplémentaire pour le maintient d'une haute efficacité de la conversion DC-DC à faible charge. Dans ce mémoire, nous présentons la conception détaillée d'un convertisseur DC-DC hautement efficace et totalement intégré dans une technologie CMOS à faible tension. Nous proposons une implémentation originale et totalement intégrée d'un convertisseur DC-DC à capacités commutés (switched capacitor - SC) opérant avec un contrôle asynchrone. L'efficacité du convertisseur est maintenue élevée en ajustant sa topologie et sa fréquence d'opération selon la charge.----------ABSTRACT Today, battery-powered portable devices are used in many applications. In applications like biomedical implants, the battery life is a major concern. Since replacing the battery of an implant needs a surgical procedure, a long battery life is a goal that all implants try to achieve. This is normally done by reducing the power dissipation in the implant's circuitry. One of the various techniques that exist for reducing the power consumption in CMOS circuitry is the dynamic voltage scaling (DVS) technique. By reducing the supply voltage, the overall power consumption of the circuits can be decreased. This technique cannot be implemented without power management blocks. The use of DC-DC converters becomes a must to save battery power. The overall power reduction can be improved by introducing high efficiency DC-DC converters. Moreover, to provide patients with the most comfort, small integrated circuits should be used in applications such as biomedical implants. The challenging aspect of designing integrated DC-DC converters is keeping the efficiency high while providing an adjustable output voltage. Additionally, devices such as electronic implants go in and out of stand-by mode to reduce power consumption. From the perspective of the DC-DC converter, the output load power is varying according to the mode of operation of the implant. This adds another challenge of sustaining the DC-DC conversion efficiency high under various loading conditions. At very light loads, preserving a high conversion efficiency is a challenge. In this master thesis, a detailed design of a high-efficiency low-voltage fully integrated DC-DC converter is presented. A unique structure of a fully integrated switched-capacitor (SC) DC-DC converter with asynchronous control is proposed. The efficiency of the converter is maintained high by adjusting the converter topology and operating frequency according to the loading conditions. The proposed SC DC-DC converter uses three different topologies to achieve three different conversion ratios. By doing so, the converter maintains high conversion efficiency at various output voltage levels. Also, an adaptive operating frequency is used by the asynchronous control to reduce efficiency losses at various loading conditions

Area- and Energy- Efficient Modular Circuit Architecture for 1,024-Channel Parallel Neural Recording Microsystem.

This research focuses to develop system architectures and associated electronic circuits for a next generation neuroscience research tool, a massive-parallel neural recording system capable of recording 1,024 channels simultaneously. Three interdependent prototypes have been developed to address major challenges in realization of the massive-parallel neural recording microsystems: minimization of energy and area consumption while preserving high quality in recordings. First, a modular 128-channel Δ-ΔΣ AFE using the spectrum shaping has been designed and fabricated to propose an area-and energy efficient solution for neural recording AFEs. The AFE achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems. It also features power and area consumption of 3.05 µW and 0.05 mm2 per channel, respectively while exhibiting 63.3 dB signal-to-noise ratio with 3.02 µVrms input referred noise. Second, an on-chip mixed signal neural signal compressor was built to reduce the energy consumption in handling and transmission of the recorded data since this occupies a large portion of the total energy consumption as the number of parallel recording increases. The compressor reduces the data rates of two distinct groups of neural signals that are essential for neuroscience research: LFP and AP without loss of informative signals. As a result, the power consumptions for the data handling and transmissions of the LFP and AP were reduced to about 1/5.35 and 1/10.54 of the uncompressed cases, respectively. In the total data handling and transmission, the measured power consumption per channel is 11.98 µW that is about 1/9 of 107.5 µW without the compression. Third, a compact on-chip dc-to-dc converter with constant 1 MHz switching frequency has been developed to provide reliable power supplies and enhance energy delivery efficiency to the massive-parallel neural recording systems. The dc-to-dc converter has only predictable tones at the output and it exhibits > 80% power conversion efficiency at ultra-light loads, < 100 µW that is relevant power most of the multi-channel neural recording systems consume. The dc-to-dc converter occupies 0.375 mm2 of area which is less than 1/20 of the area the first prototype consumes (8.64 mm2).PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/133244/1/sungyun_1.pd

Wireless Power Transfer System for Battery-Less Body Implantable Devices

Department of Electrical EngineeringAs the life expectancy is increased and the welfare is promoted, researches on the body implantable medical devices (BIMD) are actively being carried out, and products providing more various functions are being released. On the other hand, due to these various functions, the power consumption of the BIMD is also increased, so that the primary battery alone cannot provide sufficient power for the devices. The limited capacity and life time of batteries force patients to make an additional payment and suffering for the power supply of the BIMD. Wireless power transfer technology is the technology which has been making remarkable progress mainly in wireless charging for personal portable devices and electric vehicles. Convergence of wireless power transfer technology (WPT) and rechargeable battery can extend the life time of the BIMD and reduce the suffering and the cost for battery replacements. Furthermore, WPT enables the devices which do not need to operate consistently such as body implantable sensor devices to be used without batteries. In this dissertation, techniques to support WPT for BIMD are introduced and proposed. First, basic researches on magnetic coupled WPT are presented. The basics which are important factors to analyze power transmission are introduced. In addition, circuits that make up the WPT system are described. There are three common technical challenges in WPT. Those are efficiency degradation on coil geometry, voltage gain variation with coil geometry, and power losses in WPT. The common challenges are discussed in chapter II. Moreover, additional challenges which are arisen in WPT for BIMD and approaches to resolve the challenges are addressed in chapter II. Then, efficiency improvement techniques and control techniques in WPT are presented in chapter III. The presented techniques to improve efficiency are applied in coil parts and circuit parts. In coil parts, efficiency enhancement technique by geometric variation is proposed. In circuit parts, instantaneous power consuming technique for step-down converter is suggested. Li-ion battery charger is also discussed in chapter III. Additionally, the wireless controlled constant current / constant voltage charging mode and the proposed step charging method are described. After that, WPT system for BIMD is discussed one by one with the proposed techniques for each part in chapter IV. A load transformation is suggested to improve efficiency in weak coupling, and suppress voltage gain variation under coil displacement. Power conversion efficiency improvement techniques for rectifier and converter are also proposed. By using the proposed technique for the converter, we can remove the bootstrap capacitors, and reduce the overall size of power circuits. In conclusion, techniques in coil parts and circuit parts to handle challenges in WPT for BIMD are fully investigated in this thesis in addition to the efficiency improvement and control techniques in common WPT. All the techniques are verified through simulations or experiments. The approaches realized in the thesis can be applied to other applications employing the WPT.clos

Power delivery mechanisms for asynchronous loads in energy harvesting systems

PhD ThesisFor systems depending on methods, a fundamental contradiction in the power delivery chain has existed between conventional to supply it. DC/DC conversion (e.g.) has therefore been an integral part of such systems to resolve this contradiction. be made tolerant to a much wider range of Vdd variance. This may open up opportunities for much more energy efficient methods of power delivery. performance of different power delivery mechanisms driving both asynchronous and synchronous loads directly from a harvester source bypassing bulky energy method, which employs a energy from a EH circuit depending on load and source conditions, is developed. through comprehensive comparative analysis. Based on the novel CBB power delivery method, an asynchronous controller is circuits to work with tasks. The successful asynchronous control design drives a case study that is meant to explore relations between power path and task path. To deal with different tasks with variable harvested power, systems may have a range of operation conditions and thus dynamically call for CBB or SCC type power set of capacitors to form CBB or SCC is implemented with economic system size. This work presents an unconventional way of designing a compact-size, quick- circuit overcome large voltage variation in EH systems and implement smart power management for harsh EH environment. The power delivery mechanisms (SCC, employed to help asynchronous- logic-based chip testing and micro-scale EH system demonstrations