10 research outputs found
Low-complexity filter for software-defined radio by modulated interpolated coefficient decimated filter in a hybrid farrow
Realising a low-complexity Farrow channelisation algorithm for multi-standard receivers
in software-defined radio is a challenging task. A Farrow filter operates best at low frequencies
while its performance degrades towards the Nyquist region. This makes wideband channelisation
in software-defined radio a challenging task with high computational complexity. In this paper,
a hybrid Farrow algorithm that combines a modulated Farrow filter with a frequency response
interpolated coefficient decimated masking filter is proposed for the design of a novel filter with
low computational complexity. A design example shows that the HFarrow filter bank achieved
multiplier reduction of 50%, 70% and 64%, respectively, in comparison with non-uniform modulated
discrete Fourier transform (NU MDFT FB), coefficient decimated filter bank (CD FB) and interpolated
coefficient decimated (ICDM) filter algorithms. The HFarrow filter bank is able to provide the same
number of sub-band channels as other algorithms such as non-uniform modulated discrete Fourier
transform (NU MDFT FB), coefficient decimated filter bank (CD FB) and interpolated coefficient
decimated (ICDM) filter algorithms, but with less computational complexity.https://www.mdpi.com/journal/sensorsam2023Electrical, Electronic and Computer Engineerin
FPGA based Uniform Channelizer Implementation
Channelizers are widely used in modern digital communication systems.
Advanced uniform multirate channelization have been theoretically proved to be
capable of reducing the computational load, with a better performance. Therefore,
in this thesis, we implement these designs on a FPGA board for the sake of the
comprehensive evaluation of resource usage, performance and frequency
response.
The uniform filter-banks are one of the most essential unit in channelization. The
Generalised Discrete Fourier Transform Modulated Filter Bank (GDFT-FB), as an
important variant of basic a DFT-FB, has been implemented in FPGA and
demonstrated with a better computational saving rather than traditional schemes.
Moreover the oversampling version is demonstrated to have a better frequency
response with an acceptable amount of extra resources. On the other hand,
frequency response masking (FRM) techniques is able to reduce the number of
coefficients. Therefore, the full FRM GDFT-FB and alternative narrowband FRM
GDFT-FB are both implemented in FPGA platform, in order to achieve a better
performance and hardware efficiency
Low complexity and efficient dynamic spectrum learning and tunable bandwidth access for heterogeneous decentralized cognitive radio networks
International audienceThis paper deals with the design of the low complexity and efficient dynamic spectrum learning and access (DSLA) scheme for next-generation heterogeneous decentralized Cognitive Radio Networks (CRNs) such as Long Term Evolution-Advanced and 5G. Existing DSLA schemes for decentralized CRNs are focused predominantly on the decision making policies which perform the task of orthogonalization of secondary users to optimum vacant subbands of fixed bandwidth. The focus of this paper is the design of DSLA scheme for decentralized CRNs to support the tunable vacant bandwidth requirements of the secondary users while minimizing the computationally intensive subband switchings. We first propose a new low complexity VDF which is designed by modifying second order frequency transformation and subsequently combining it with the interpolation technique. It is referred to as Interpolation and Modified Frequency Transformation based VDF (IMFT-VDF) and it provides tunable bandpass responses anywhere over Nyquist band with complete control over the bandwidth as well as the center frequency. Second, we propose a tunable decision making policy, ρt_randρt_rand, consisting of learning and access unit, and is designed to take full advantage of exclusive frequency response control offered by IMFT-VDF. The simulation results verify the superiority of the proposed DSLA scheme over the existing DSLA schemes while complexity comparisons indicate total gate count savings from 11% to as high as 87% over various existing schemes. Also, lower number of subband switchings make the proposed scheme power-efficient and suitable for battery-operated cognitive radio terminals
A New Low Complexity Uniform Filter Bank Based on the Improved Coefficient Decimation Method
In this paper, we propose a new uniform filter bank (FB) based on the improved coefficient decimation method (ICDM). In the proposed FB’s design, the ICDM is used to obtain different multi-band frequency responses using a single lowpass prototype filter. The desired subbands are individually obtained from these multi-band frequency responses by using low order frequency response masking filters and their corresponding ICDM output frequency responses. We show that the proposed FB is a very low complexity alternative to the other FBs in literature, especially the widely used discrete Fourier transform based FB (DFTFB) and the CDM based FB (CDFB). The proposed FB can have a higher number of subbands with twice the center frequency resolution when compared with the CDFB and DFTFB. Design example and implementation results show that our FB achieves 86.59% and 58.84% reductions in resource utilizations and 76.95% and 47.09% reductions in power consumptions when compared with the DFTFB and CDFB respectively
Channelization for Multi-Standard Software-Defined Radio Base Stations
As the number of radio standards increase and spectrum resources come under more pressure, it becomes ever less efficient to reserve bands of spectrum for exclusive use by a single radio standard. Therefore, this work focuses on channelization structures compatible with spectrum sharing among multiple wireless standards and dynamic spectrum allocation in particular. A channelizer extracts independent communication channels from a wideband signal, and is one of the most computationally expensive components in a communications receiver. This work specifically focuses on non-uniform channelizers suitable for multi-standard Software-Defined Radio (SDR) base stations in general and public mobile radio base stations in particular.
A comprehensive evaluation of non-uniform channelizers (existing and developed during the course of this work) shows that parallel and recombined variants of the Generalised Discrete Fourier Transform Modulated Filter Bank (GDFT-FB) represent the best trade-off between computational load and flexibility for dynamic spectrum allocation. Nevertheless, for base station applications (with many channels) very high filter orders may be required, making the channelizers difficult to physically implement.
To mitigate this problem, multi-stage filtering techniques are applied to the GDFT-FB. It is shown that these multi-stage designs can significantly reduce the filter orders and number of operations required by the GDFT-FB. An alternative approach, applying frequency response masking techniques to the GDFT-FB prototype filter design, leads to even bigger reductions in the number of coefficients, but computational load is only reduced for oversampled configurations and then not as much as for the multi-stage designs. Both techniques render the implementation of GDFT-FB based non-uniform channelizers more practical.
Finally, channelization solutions for some real-world spectrum sharing use cases are developed before some final physical implementation issues are considered
Energy-efficient hardware architecture and vlsi implementation of a polyphase channelizer with applications to subband adaptive filtering
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementation of polyphase channelizer, integrating algorithmic, architectural and circuit level design techniques. At algorithm level, low complexity polyphase channelizer architecture is derived using multirate signal processing approach. To reduce the computational complexity in polyphase filters, computation sharing differential coefficient (CSDC) method is effectively used as an architectural level technique. The main idea of CSDC is to combine the strength of augmented differential coefficient method and subexpression sharing. Efficient circuitlevel techniques: low power commutator implementation, dual-VDD scheme and novel level-converting flip-flop (LCFF), are also used to further reduce the power dissipation. The proposed polyphase channelizer consumes 352 mW power with throughput of 480 million samples per second (MSPS). A test chip has been fabricated in 0.18 μm CMOS technology and its functionality is verified. Chip measurement results show that the dual-VDD implementation achieves a total power saving of 2.7 X