A Low Total Harmonic Distortion Sinusoidal Oscillator Based on Digital Harmonic Cancellation Technique

Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later

A Low Total Harmonic Distortion Sinusoidal Oscillator Based on Digital Harmonic Cancellation Technique

Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later

Analog sinewave signal generators for mixed-signal built-in test applications

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators—a continuous-time generator and a discrete-time one—have been integrated in a standard 0.35 μm CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.Gobierno de España TEC2007-68072/MIC, TSI-020400-2008-71/MEDEA+2A105, CATRENE CT302Junta de Andalucía P09-TIC-538

A 1V 8th-order 250MHz current-mode butterworth lowpass filter

Continuous-time filters can be used as preprocessing blocks in front of an analog-to-digital converter (A/D) in the receiving data path of a disk-drive read-channel system and as post processing blocks after a digital system. High-frequency continuous-time filters with low supply voltage are finding increased applications in high-speed Integrated Circuits (ICs) of telecommunication, video, and magnetic read-channel. This has been the driving force in the development of numerous continuous-time filter techniques exist today, and further ongoing research. Among the different topologies, current-mode functions exhibit higher frequency potential, simpler architectures, and lower supply voltage capabilities. Active RC filters have been used for years due to the high linearity. However, the uncertainty in cutoff frequency, mainly due to the integrated passive resistors and capacitors, limits the application. On the other hand, current conveyors, introduced in the early 1970\u27s, are now emerging as an important class of circuits. A novel current-mode active-RC filter combines the advantages of current conveyor circuits and active RC filter configuration with digital frequency tuning is proposed. With digital tuning, the fabricated central frequency is measured with respect to a provided reference frequency, and a digital code is then derived which selects the appropriate capacitor elements that will return tuning to the nominal value, within some defined tolerance (e.g., ±5%). A 1V 8th order 25OMhz current-mode Butterworth lowpass filter with digital frequency tuning has been implemented in TSMC 0.25[Mu]m CMOS technology

Built-in self test of high speed analog-to-digital converters

Signals found in nature need to be converted to the digital domain through analog-to-digital converters (ADCs) to be processed by digital means [1]. For applications in communication and measurement [2], [3], high conversion rates are required. With advances of the complementary metal oxide semiconductor (CMOS) technology, the conversion rates of CMOS ADCs are now well beyond the gigasamples per second (GS/s) range, but only moderate resolutions are required [4]. These ADCs need to be tested after fabrication and, if possible, during field operation. The test costs are a very significant fraction of their production cost [5]. This is mainly due to lengthy use of very expensive automated test equipment (ATE) to apply specific test stimuli to the devices under test (DUT) and to collect and analyze their responses.publishe

Time-Mode Analog Circuit Design for Nanometric Technologies

Rapid scaling in technology has introduced new challenges in the realm of traditional analog design. Scaling of supply voltage directly impacts the available voltage-dynamic-range. On the other hand, nanometric technologies with fT in the hundreds of GHz range open opportunities for time-resolution-based signal processing. With reduced available voltage-dynamic-range and improved timing resolution, it is more convenient to devise analog circuits whose performance depends on edge-timing precision rather than voltage levels. Thus, instead of representing the data/information in the voltage-mode, as a difference between two node voltages, it should be represented in time-mode as a time-difference between two rising and/or falling edges. This dissertation addresses the feasibility of employing time-mode analog circuit design in different applications. Specifically: 1) Time-mode-based quanitzer and feedback DAC of SigmaDelta ADC. 2) Time-mode-based low-THD 10MHz oscillator, 3) A Spur-Frequency Boosting PLL with -74dBc Reference-Spur Rejection in 90nm Digital CMOS. In the first project, a new architectural solution is proposed to replace the DAC and the quantizer by a Time-to-Digital converter. The architecture has been fabricated in 65nm and shows that this technology node is capable of achieving a time-matching of 800fs which has never been reported. In addition, a competitive figure-of-merit is achieved. In the low-THD oscillator, I proposed a new architectural solution for synthesizing a highly-linear sinusoidal signal using a novel harmonic rejection approach. The chip is fabricated in 130nm technology and shows an outstanding performance compared to the state of the art. The designed consumes 80% less power; consumes less area; provides much higher amplitude while being composed of purely digital circuits and passive elements. Last but not least, the spur-frequency boosting PLL employs a novel technique that eliminates the reference spurs. Instead of adding additional filtering at the reference frequency, the spur frequency is boosted to higher frequency which is, naturally, has higher filtering effects. The prototype is fabricated in 90nm digital CMOS and proved to provide the lowest normalized reference spurs ever reported

On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform

Nowadays, the rapid development of system-on-chip (SoC) market introduces tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC fabrication process is scaling down to allow higher density of integration but makes the chips more sensitive to the process-voltage-temperature (PVT) variations. A successful IC product not only imposes great pressure on the IC designers, who have to handle wider variations and enforce more design margins, but also challenges the test procedure, leading to more check points and longer test time. To relax the designers’ burden and reduce the cost of testing, it is valuable to make the IC chips able to test and tune itself to some extent. In this dissertation, a fully integrated in-situ design validation and optimization (VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test (BIST) techniques for analog circuits. Based on the data collected from BIST, the error between the measured and the desired performance of the target circuit is evaluated using a cost function. A digital multi-dimensional optimization engine is implemented to adaptively adjust the analog circuit parameters, seeking the minimum value of the cost function and achieving the desired performance. To verify this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip. Apart from the VO system, several improved BIST techniques are also proposed in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration. Moreover, an on-chip RF receiver linearity BIST methodology for continuous and discrete-time hybrid baseband chain is proposed. The proposed receiver chain implements a charge-domain FIR filter to notch the two excitation signals but expose the third order intermodulation (IM3) tones. It simplifies the linearity measurement procedure–using a power detector is enough to analyze the receiver’s linearity. Finally, a low cost fully digital built-in analog tester for linear-time-invariant (LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to measure the delays corresponded to a ramp excitation signal and is able to estimate the pole or zero locations of a low-pass LTI system

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

High performance continuous-time filters for information transfer systems

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications