An X-Band power amplifier design for on-chip RADAR applications

Tremendous growth of RAdio Detecting And Ranging (RADAR) and communication electronics require low manufacturing cost, excellent performance, minimum area and highly integrated solutions for transmitter/receiver (T/R) modules, which are one of the most important blocks of RADAR systems. New circuit topologies and process technologies are investigated to fulfill these requirements of next generation RADAR systems. With the recent improvements, Silicon-Germanium Bipolar CMOS technology became a good candidate for recently used III-V technologies, such as GaAs, InP, and GaN, to meet high speed and performance requirements of present RADAR applications. As new process technologies are used, new solutions and circuit architectures have to be provided while taking into account the advantages and disadvantageous of used technologies. In this thesis, a new T/R module system architecture is presented for single/onchip X-Band phased array RADAR applications. On-chip T/R module consists of five blocks; T/R switch, single-pole double-throw (SPDT) switch, low noise amplifier (LNA), power amplifier (PA), and phase shifter. As the main focus of this thesis, a two-stage power amplifier is realized, discussed and measured. Designed in IHP's 0.25 [micrometer] SiGe BiCMOS process technology, the power amplifier operates in Class-A mode to achieve high linearity and presents a measured small-signal gain of 25 dB at 10 GHz. While achieving an output power of 22 dBm, the power amplifier has drain efficiency of 30 % in saturation. The total die area is 1 [square millimeters], including RF and DC pads. To our knowledge, these results are comparable to and/or better than those reported in the literature

SiGe BiCMOS front-end circuits for X-Band phased arrays

The current Transmit/Receive (T/R) modules have typically been implemented using GaAs- and InP-based discrete monolithic microwave integrated circuits (MMIC) to meet the high performance requirement of the present X-Band phased arrays. However their cost, size, weight, power consumption and complexity restrict phased array technology only to certain military and satellite applications which can tolerate these limitations. Therefore, next generation X-Band phased array radar systems aim to use low cost, silicon-based fully integrated T/R modules. For this purpose, this thesis explores the design of T/R module front-end building blocks based on new approaches and techniques which can pave the way for implementation of fully integrated X-Band phased arrays in low-cost SiGe BiCMOS process. The design of a series-shunt CMOS T/R switch with the highest IP1dB, compared to other reported works in the literature is presented. The design focuses on the techniques, primarily, to achieve higher power handling capability (IP1dB), along with higher isolation and better insertion loss of the T/R switch. Also, a new T/R switch was implemented using shunt NMOS transistors and slow-wave quarter wavelength transmission lines. It presents the utilization of slow-wave transmissions lines in T/R switches for the first time in any BiCMOS technology to the date. A fully integrated DC to 20 GHz SPDT switch based on series-shunt topology was demonstrated. The resistive body oating and on-chip impedance transformation networks (ITN) were used to improve power handling of the switch. An X-Band high performance low noise ampli er (LNA) was implemented in 0.25 μm SiGe BiCMOS process. The LNA consists of inductively degenerated two cascode stages with high speed SiGe HBT devices to achieve low noise gure (NF), high gain and good matching at the input and output, simultaneously. The performance parameters of the LNA collectively constitute the best Figure-of-Merit value reported in similar technologies, to the best of author's knowledge. Furthermore, a switched LNA was implemented SiGe BiCMOS process for the first time at X-Band. The resistive body floating technique was incorporated in switched LNA design, for the first time, to improve the linearity of the circuit further in bypass mode. Finally, a complete T/R module with a state-of-the-art performance was implemented using the individually designed blocks. The simulations results of the T/R module is presented in the dissertation. The state-of-the-art performances of the presented building blocks and the complete module are attributed to the unique design methodologies and techniques

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio