3 research outputs found
A High Efficiency DC/DC Converter for High Voltage Gain High Current Applications
A new class of high-voltage-gain dc-dc converters for high-efficiency and transformer-less dc-dc applications, where large voltage step-up ratios are required, is presented in this paper. The converter is derived from the hybrid integration of a switched-capacitor converter and a boost converter. It features high step-up voltage conversion ratio with a moderate duty cycle, nonpulsating input current, low-voltage stress on all of the switches, easy implementation of control and driving circuits, scalability for high-current high-power applications, and low cost due to reduced components via combination of a two-stage converter into a single-stage converter. Full soft-charging operation and minimal device voltage stresses are achieved under all operating conditions. Steady-state operations of the converter are comprehensively analyzed. A 300-W prototype of a 19-time converter achieving the peak efficiency of 96.1% is built. Both simulation and experimental results validating the theoretical analysis and operation of the converter are provided.</p
Analysis and design of switched-capacitor DC-DC converters with discrete event models
Ph. D. Thesis.Switched-capacitor DC-DC converters (SCDDCs) play a critical role in low power
integrated systems. The analysis and design processes of an SCDDC impact the
performance and power efficiency of the whole system. Conventionally, researchers carry
out the analysis and design processes by viewing SCDDCs as analogue circuits. Analogue
attributes of an SCDDC, such as the charge flow current or the equivalent output impedance,
have been studied in considerable detail for performance enhancement. However, in most
existing work, less attention is paid to the analysis of discrete events (e.g. digital signal
transitions) and the relationships between discrete events in SCDDCs. These discrete
events and the relationships between discrete events also affect the performance of
SCDDCs. Certain negative effects of SCDDCs such as leakage current are introduced by
unhealthy discrete states. For example, MOS devices in an SCDDC could conduct
undesirably under certain combinations of signals, resulting in reversion losses (a type of
leakage in SCDDCs). However, existing work only use verbal reasoning and waveform
descriptions when studying these discrete events, which may cause confusion and result in
an informal design process consisting of intuitive design and backed up merely by
validation based on natural language discussions and simulations. There is therefore a need
for formalised methods to describe and analyse these discrete events which may facilitate
systematic design techniques.
This thesis presents a new method of analysing and designing SCDDCs using discrete event
models. Discrete event models such as Petri nets and Signal Transition Graphs (STGs) are
commonly used in asynchronous circuits to formally describe and analyse the relationships
between discrete transitions. Modelling SCDDCs with discrete event models provides a
formal way to describe the relations between discrete transitions in SCDDCs. These
discrete event models can be used for analysis, verification and even design guidance for
SCDDC design. The rich set of existing analysis methods and tools for discrete event
models could be applied to SCDDCs, potentially improving the analysis and design flow
for them. Moreover, since Petri nets and STGs are generally used to analyse and design
asynchronous circuits, modelling and designing SCDDCs with STG models may
additionally facilitate the incorporation of positive features of asynchronous circuits in
SCDDCs (e.g. no clock skew). In this thesis, the relations between discrete events in SCDDCs are formally described with
SC-STG (an extended STG targeting multi-voltage systems, to which SCDDCs belong),
which avoids the potential confusion due to natural language and waveform descriptions.
Then the concurrency and causality relations described in SC-STG model are extended to
Petri nets, with which the presence of reversion losses can be formally determined and
verified. Finally, based on the STG and Petri net models, a new design method for
reversion-loss-free SCDDCs is proposed. In SCDDCs designed with the new method,
reversion losses are entirely removed by introducing asynchronous controls, synthesised
with the help of a software synthesis toolkit “Workcraft”.
To demonstrate the analysis capabilities of the method, several cross-coupled voltage
doublers (a type of SCDDC) are analysed and studied with discrete event models as
examples in this thesis. To demonstrate the design capabilities of the method, a new
reversion-loss-free cross-coupled voltage doubler is designed. The cross-coupled voltage
doubler is widely used in low power integrated systems such as flash memories, LCD
drivers and wireless energy harvesting systems. The proposed modelling method is
potentially used in both research and industrial area of those applications for a formal and
high-efficiency design proces