Millimetre Wave Series Connected Doherty PA Using 45nm SOI Process

With the high demand for high data rate communication systems, it is expected that wireless networks will migrate into the unexploited millimeter-wave frequencies. This migration and the utilization of wide-band digitally modulated signal possessing of high Peak-to-Average-Power- Ratio (PAPR) brings diffcult challenges in attaining a satisfactory trade-off between linearity and efficiency when designing mm-wave power amplifiers (PAs). There are various methods of maximizing the output power and peak effciency of mm-wave PAs that use deep-sub-micron technologies. Of these methods, little attention has been given to the efficiency enhancement of PAs in back-off region. The use of the Doherty technique in the mm-wave frequencies has attracted little attention. This is mainly due to complexity in realizing the quarter-wave impedance inverter and the low-gain of the class-C operating peaking transistor using deep-sub-micron technologies. In this thesis, a series-connected-load (SCL) Doherty topology is proposed to enhance the efficiency of a millimeter-wave power amplifier realized on a deep-sub-micron semiconductor technology. The output combiner is determined by the ABCD matrices of the ideal combiner network in the SCL Doherty PA to ensure proper load modulation. Then, it describes the methodology applied to realize the transformer-based combiner networks while absorbing the parasitic capacitance of the transistors to maximize efficiency in the back-off region. This methodology is then applied to realize a two-stage SCL Doherty PA in 45 nm Silicon-on- Insulator CMOS technology to operate at 60 GHz

CMOS MESFET Cascode Amplifiers for RFIC Applications

abstract: There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201