A High-Performance and Low-Complexity 5G LDPC Decoder: Algorithm and Implementation

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR blocklengths and code rates, which is a significant challenge. In this paper, we present a high-performance and low-complexity LDPC decoder, tailor-made to fulfill the 5G requirements. First, to close the gap between belief propagation (BP) decoding and its approximations in hardware, we propose an extension of adjusted min-sum decoding, called generalized adjusted min-sum (GA-MS) decoding. This decoding algorithm flexibly truncates the incoming messages at the check node level and carefully approximates the non-linear functions of BP decoding to balance the error-rate and hardware complexity. Numerical results demonstrate that the proposed fixed-point GAMS has only a minor gap of 0.1 dB compared to floating-point BP under various scenarios of 5G standard specifications. Secondly, we present a fully reconfigurable 5G NR LDPC decoder implementation based on GA-MS decoding. Given that memory occupies a substantial portion of the decoder area, we adopt multiple data compression and approximation techniques to reduce 42.2% of the memory overhead. The corresponding 28nm FD-SOI ASIC decoder has a core area of 1.823 mm2 and operates at 895 MHz. It is compatible with all 5G NR LDPC codes and achieves a peak throughput of 24.42 Gbps and a maximum area efficiency of 13.40 Gbps/mm2 at 4 decoding iterations.Comment: 14 pages, 14 figure

5G NR-V2X: Towards Connected and Cooperative Autonomous Driving

This paper is concerned with the key features and fundamental technology components for 5G New Radio (NR) for genuine realization of connected and cooperative autonomous driving. We discuss the major functionalities of physical layer, Sidelink features and its resource allocation, architecture flexibility, security and privacy mechanisms, and precise positioning techniques with an evolution path from existing cellular vehicle-to-everything (V2X) technology towards NR-V2X. Moreover, we envisage and highlight the potential of machine learning for further enhancement of various NR-V2X services. Lastly, we show how 5G NR can be configured to support advanced V2X use cases in autonomous driving

FPGA accelerator of algebraic quasi cyclic LDPC codes for NAND flash memories

In this article, the authors implement an FPGA simulator that accelerates the performance evaluation of very long QC-LDPC codes, and present a novel 8-KB LDPC code for NAND flash memory with better performance

A Brief Overview of CRC Implementation for 5G NR

In fifth generation (5G) new radio (NR), the medium access control (MAC) layer organizes the data into the transport block and transmits it to the physical layer. The transport block consists of up to million bits. When the transport block size exceeds a threshold, the transport block is divided into multiple equal size code blocks. The code block consists of up to 8448 bits. Both the transport block and the code block have a cyclic redundancy check (CRC) attached. Due to the difference in the size of the transport block and the code block, the CRC processing scheme suitable for the transport block and that suitable for the code block are different. This chapter gives an overview of the CRC implementation in 5G NR

Low Power Low-Density Parity Check Encoder Using Dynamic Voltage and Frequency Scaling Approach

Low-Density Parity Check (LDPC) codes are viewed as one of the best error correction coding (ECC) methods in terms of correction efficiency. They have been used in several modern data transmission standards, where the codecs are often built inside specialized integrated circuits (ICs). On the other hand, Complementary Metal-Oxide-Semiconductor (CMOS) circuits have evolved as a critical design characteristic that the designer must consider such as power, which has been overlooked by many researchers. For that reason, in this paper, a research work that reduces LDPC encoder power consumption is presented using a well-known power reduction method named Dynamic Voltage and Frequency Scaling (DVFS), which is one of the most powerful power reduction strategies in CMOS circuits. The proposed system includes a fuzzy logic controller with the DVFS technique to control and select the optimum level of voltage that enters the encoder to reduce its total power consumption. This combination of these two techniques showed significant power reduction and control while causing no impact on the LDPC efficiency, flexibility, and performance. Comparisons with other studies covering power reduction in LDPC codes have shown that the purposed system has the best performance over similar systems in the literature

An efficient reconfigurable code rate cooperative low-density parity check codes for gigabits wide code encoder/decoder operations

In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz