The Design of a 24-bit Hardware Gaussian Noise Generator via the Box-Muller Method and its Error Analysis

In regards to data transmission in communication systems, there is need for robust emulation of communication channels via Gaussian noise generation. Over time, larger sample sizes are desired to reach farther into the tail ends of the distribution and faster sample generation speeds are desired versus the software implementations. This paper proposes a Gaussian noise generator utilizing the Box-Muller method written in Verilog HDL targeting a 65nm ASIC process utilizing Synopsys Design Compiler. The design creates two 24-bit noise samples per clock cycle and each sample is accurate to one unit in the last place. A sample can represent up to 9.42σ, which allows for a sample size of 2 · 1020. The design generates 800 million samples/s at a clock frequency of 400MHz. After a thorough error analysis, a bit-exact model was created in MATLAB and a thorough probability and statistic analysis was executed on the generated sample sets

Performance Analysis of a Chaos-Based Multi-User Communication System Implemented in DSP Technology

This paper presents the implementation of a multi-user chaos-based communication system in DSP. The system is based on the chaotic phase shift keying (CPSK) digital modulation scheme, where chaotic signals are used as the spreading sequences of a CDMA system. Using chaotic signals offers the advantages of increased security and higher system capacity compared with conventional sequences. The aim of this hardware implementation was to enable a comparison against analytical performance results for CPSK. The transceiver prototype was implemented on a 32-bit floating-point TigerSHARC DSP. Its bit error rate (BER) characteristics were measured in the presence of additive white Gaussian noise. The prototype achieves excellent BER performance, matching that of theoretical CPSK. The effects of the limited number precision of the hardware platform are thus negligible. However, due to the limited concurrency of DSP, the multi-user system only supports low data rates

DSP Prototype of a Chaos-Based Multi-User Communication System: Design and Performance Analysis

This paper presents the implementation of a multi-user chaos-based communication system in DSP (digital signal processor) technology. The system is based on the chaotic phase shift keying (CPSK) digital modulation scheme, where chaotic signals are used as the spreading sequences of a CDMA (code division multiple access) system. Using chaotic signals offers the advantages of increased security and higher system capacity compared with conventional sequences. The aim of this hardware implementation was to enable a comparison against analytical performance results for CPSK. The transceiver prototype was implemented on a 32-bit floating-point TigerSHARC DSP. Its bit error rate (BER) characteristics were measured in the presence of additive white Gaussian noise. The prototype achieves excellent BER performance, matching that of theoretical CPSK. The effects of the limited number precision of the hardware platform are thus negligible. However, due to the limited concurrency of DSP, the multi-user system only supports low data rates. Despite this, the prototype demonstrates that the CPSK scheme is a promising and viable CDMA option for the future

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Design Exploration of an FPGA-Based Multivariate Gaussian Random Number Generator

Monte Carlo simulation is one of the most widely used techniques for computationally intensive simulations in a variety of applications including mathematical analysis and modeling and statistical physics. A multivariate Gaussian random number generator (MVGRNG) is one of the main building blocks of such a system. Field Programmable Gate Arrays (FPGAs) are gaining increased popularity as an alternative means to the traditional general purpose processors targeting the acceleration of the computationally expensive random number generator block due to their fine grain parallelism and reconfigurability properties and lower power consumption. As well as the ability to achieve hardware designs with high throughput it is also desirable to produce designs with the flexibility to control the resource usage in order to meet given resource constraints. This work proposes a novel approach for mapping a MVGRNG onto an FPGA by optimizing the computational path in terms of hardware resource usage subject to an acceptable error in the approximation of the distribution of interest. An analysis on the impact of the error due to truncation/rounding operation along the computational path is performed and an analytical expression of the error inserted into the system is presented. Extra dimensionality is added to the feature of the proposed algorithm by introducing a novel methodology to map many multivariate Gaussian random number generators onto a single FPGA. The effective resource sharing techniques introduced in this thesis allows further reduction in hardware resource usage. The use of MVGNRG can be found in a wide range of application, especially in financial applications which involve many correlated assets. In this work it is demonstrated that the choice of the objective function employed for the hardware optimization of the MVRNG core has a considerable impact on the final performance of the application of interest. Two of the most important financial applications, Value-at-Risk estimation and option pricing are considered in this work

Design and Implementation of a Re-Configurable Arbitrary Signal Generator and Radio Frequency Spectrum Analyser

This research is focused on the design, simulation and implementation of a reconfigurable arbitrary signal generator and the design, simulation and implementation of a radio frequency spectrum analyser based on digital signal processing. Until recently, Application Specific Integrated Circuits (ASICs) were used to produce high performance re-configurable function and arbitrary waveform generators with comprehensive modulation capabilities. However, that situation is now changing with the availability of advanced but low cost Field Programmable Gate Arrays (FPGAs), which could be used as an alternative to ASICs in these applications. The availability of high performance FPGA families opens up the opportunity to compete with ASIC solutions at a fraction of the development cost of an ASIC solution. A fast digital signal processing algorithm for digital waveform generation, using primarily but not limited to Direct Digital Synthesis (DDS) technologies, developed and implemented in a field-configurable logic, with control provided by an embedded microprocessor replacing a high cost ASIC design appeared to be a very attractive concept. This research demonstrates that such a concept is feasible in its entirety. A fully functional, low-complexity, low cost, pulse, Gaussian white noise and DDS based function and arbitrary waveform generator, capable of being amplitude, frequency and phase modulated by an internally generated or external modulating signal was implemented in a low-cost FPGA. The FPGA also included the capabilities to perform pulse width modulation and pulse delay modulation on pulse waveforms. Algorithms to up-convert the sampling rate of the external modulating signal using Cascaded Integrator Comb (CIC) filters and using interpolation method were analysed. Both solutions were implemented to compare their hardware complexities. Analysis of generating noise with user-defined distribution is presented. The ability of triggering the generator by an internally generated or an external event to generate a burst of waveforms where the time between the trigger signal and waveform output is fixed was also implemented in the FPGA. Finally, design of interface to a microprocessor to provide control of the versatile waveform generator was also included in the FPGA. This thesis summarises the literature, design considerations, simulation and implementation of the generator design. The second part of the research is focused on radio frequency spectrum analysis based on digital signal processing. Most existing spectrum analysers are analogue in nature and their complexity increases with frequency. Therefore, the possibility of using digital techniques for spectrum analysis was considered. The aim was to come up with digital system architecture for spectrum analysis and to develop and implement the new approach on a suitable digital platform. This thesis analyses the current literature on shifting algorithms to remove spurious responses and highlights its drawbacks. This thesis also analyses existing literature on quadrature receivers and presents novel adaptation of the existing architectures for application in spectrum analysis. A wide band spectrum analyser receiver with compensation for gain and phase imbalances in the Radio Frequency (RF) input range, as well as compensation for gain and phase imbalances within the Intermediate Frequency (IF) pass band complete with Resolution Band Width (RBW) filtering, Video Band Width (VBW) filtering and amplitude detection was implemented in a low cost FPGA. The ability to extract the modulating signal from a frequency or amplitude modulated RF signal was also implemented. The same family of FPGA used in the generator design was chosen to be the digital platform for this design. This research makes arguments for the new architecture and then summarises the literature, design considerations, simulation and implementation of the new digital algorithm for the radio frequency spectrum analyser

Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder

The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into the statistics of a channel emulator and analyzes its effects on a particular decoder