An architecture and execution environment for component integration rules

The Integration Rules (IRules) project at Arizona State University (http://www.eas.asu.edu/~irules) is developing a declarative event-based approach to component integration. Integration rules are based on the concept of active database rules, providing an active approach for specifying event- driven activity in a distributed environment. The IRules project consists of a knowledge model that specifies the IRules Definition Language and an execution model that supports integration rule execution. This research focuses on the execution model and the architectural design parts of the IRules project. The main objective of this research is to develop a distributed execution environment for using integration rules in the integration of black-box components. In particular, this research will investigate the design of an architecture that supports the IRules semantic framework, the development of an execution model for rule and transaction processing, and the design of a rule processing algorithm for coordinating the execution of integration rules. This research will combine the distributed computing framework of Jini, the asynchronous event notification mechanism of the Java Message Service (JMS), and the distributed blocking access functionality of JavaSpaces to support active rule processing in a distributed environment. The limitations of the underlying Enterprise JavaBeans (EJB) component model pose transaction processing challenges for the integration process. This research will develop a suitable transaction model and processing logic to overcome the limitations of the underlying EJB component model. Furthermore, the architectural design will allow an easy extension of the system to accommodate other component models. This research is expected to contribute to nested rule and transaction processing for active rules that have not been previously addressed in distributed rule processing environments. The development of the IRules execution environment will also contribute to the use of distributed rule- based techniques for eventdriven component integration

Making deductive database a practical technology : a step forward

Projet SABREDeductive databases provide a formal framework to study rule-based query languages that are extensions of first-order logic. However, deductive database languages and their current implementations do not seem appropriate for improving the development of real applications or even sample of them. Our goal is to make deductive databases a practical technology. The design and implementation of the RDL1 system, presented in this paper, constitute a step toward this goal. Our approach is based on the integration of a production rule language within a relational database system, the development of a rule-based programming environment and the support of system extensibility using abstract data types facility. We present important lessons learned during the implementation of the system. Also, comparisons with related work such as LDL, STARBURST and POSTGRES are given

An ontology framework for developing platform-independent knowledge-based engineering systems in the aerospace industry

This paper presents the development of a novel knowledge-based engineering (KBE) framework for implementing platform-independent knowledge-enabled product design systems within the aerospace industry. The aim of the KBE framework is to strengthen the structure, reuse and portability of knowledge consumed within KBE systems in view of supporting the cost-effective and long-term preservation of knowledge within such systems. The proposed KBE framework uses an ontology-based approach for semantic knowledge management and adopts a model-driven architecture style from the software engineering discipline. Its phases are mainly (1) Capture knowledge required for KBE system; (2) Ontology model construct of KBE system; (3) Platform-independent model (PIM) technology selection and implementation and (4) Integration of PIM KBE knowledge with computer-aided design system. A rigorous methodology is employed which is comprised of five qualitative phases namely, requirement analysis for the KBE framework, identifying software and ontological engineering elements, integration of both elements, proof of concept prototype demonstrator and finally experts validation. A case study investigating four primitive three-dimensional geometry shapes is used to quantify the applicability of the KBE framework in the aerospace industry. Additionally, experts within the aerospace and software engineering sector validated the strengths/benefits and limitations of the KBE framework. The major benefits of the developed approach are in the reduction of man-hours required for developing KBE systems within the aerospace industry and the maintainability and abstraction of the knowledge required for developing KBE systems. This approach strengthens knowledge reuse and eliminates platform-specific approaches to developing KBE systems ensuring the preservation of KBE knowledge for the long term

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized