A Low Jitter Wideband Fractional-N Subsampling Phase Locked Loop (SSPLL)

Frequency synthesizers have become a crucial building block in the evolution of modern communication systems and consumer electronics. The spectral purity performance of frequency synthesizers limits the achievable data-rate and presents a noise-power tradeoff. For communication standards such as LTE where the channel spacing is a few kHz, the synthesizers must provide high frequencies with sufficiently wide frequency tuning range and fine frequency resolutions. Such stringent performance must be met with a limited power and small chip area. In this thesis a wideband fractional-N frequency synthesizer based on a subsampling phase locked loop (SSPLL) is presented. The proposed synthesizer which has a frequency resolution less than 100Hz employs a digital fractional controller (DFC) and a 10-bit digital-to-time converter (DTC) to delay the rising edges of the reference clock to achieve fractional phase lock. For fast convergence of the delay calibration, a novel two-step delay correlation loop (DCL) is employed. Furthermore, to provide optimum settling and jitter performance, the loop transfer characteristics during frequency acquisition and phase-lock are decoupled using a dual input loop filter (DILF). The fractional-N sub-sampling PLL (FNSSPLL) is implemented in a TSMC 40nm CMOS technology and occupies a total active area of 0.41mm^2. The PLL operates over frequency range of 2.8 GHz to 4.3 GHz (42% tuning range) while consuming 9.18mW from a 1.1V supply. The integrated jitter performance is better than 390 fs across all fractional frequency channel. The worst case fractional spur of -48.3 dBc occurs at a 650 kHz offset for a 3.75GHz fractional channel. The in-band phase noise measured at a 200 kHz offset is -112.5 dBc/Hz

A Novel Three-Point Modulation Technique for Fractional-N Frequency Synthesizer Applications

This paper presents a novel three-point modulation technique for fractional-N frequency synthesizer applications. Convention modulated fractional-N frequency synthesizers suffer from quantization noise, which degrades not only the phase noise performance but also the modulation quality. To solve this problem, this work proposes a three-point modulation technique, which not only cancels the quantization noise, but also markedly boosts the channel switching speed. Measurements reveal that the implemented 2.4 GHz fractional-N frequency synthesizer using three-point modulation can achieve a 2.5 Mbps GFSK data rate with an FSK error rate of only 1.4 %. The phase noise is approximately -98 dBc/Hz at a frequency offset of 100 kHz. The channel switching time is only 1.1 μs with a frequency step of 80 MHz. Comparing with conventional two-point modulation, the proposed three-point modulation greatly improves the FSK error rate, phase noise and channel switching time by about 10 %, 30 dB and 126 μs, respectively

A fully integrated multiband frequency synthesizer for WLAN and WiMAX applications

This paper presents a fractional N frequency synthesizer which covers WLAN and WiMAX frequencies on a single chip. The synthesizer is fully integrated in 0.35μm BiCMOS AMS technology except crystal oscillator. The synthesizer operates at four frequency bands (3.101-3.352GHz, 3.379-3.727GHz, 3.7-4.2GHz, 4.5-5.321GHz) to provide the specifications of 802.16 and 802.11 a/b/g/y. A single on-chip LC - Gm based VCO is implemented as the core of this synthesizer. Different frequency bands are selected via capacitance switching and fine tuning is done using varactor for each of these bands. A bandgap reference circuit is implemented inside of this charge pump block to generate temperature and power supply independent reference currents. Simulated settling time is around 10μsec. Total power consumption is measured to be 118.6mW without pad driving output buffers from a 3.3V supply. The phase noise of the oscillator is lower than -116.4dbc/Hz for all bands. The circuit occupies 2.784 mm2 on Si substrate, including DC, Digital and RF pads

A Programmable Frequency Divider Having a Wide Division Ratio Range, and Close-to-50% Output Duty-Cycle

In Radio Frequency (RF) integrated circuit design field, programmable dividers are getting more and more attentions in recent years. A programmable frequency divider can divide an input frequency by programmable ratios [1]. It is a key component of a frequency synthesizer. It also can be used to generate variable clock-signals for: switched-capacitor filters (SCFs), digital systems with different power-states, as well as multiple clock-signals on the same system-on-a-chip (SOC). These circuits need high performance programmable frequency dividers, operating at high frequencies and having wide division ratio ranges, with binary division ratio controls and 50% output duty-cycle. Different types of programmable frequency dividers are reviewed and compared. A programmable frequency divider with a wide division ratio range of (8 ~ 524287) has been reported [2]. Because the output duty-cycle of this reported divider is far from 50%, the circuit in [2] has very limited applications. The proposed design solves this problem, without compromising other advantages of the design in [2]. The proposed design is fabricated in a 0.18-μm RF CMOS process. Test results show that the output duty-cycle is 50% when the division ratio is an even number. The duty-cycle is 44.4% when the division ratio is 9. The output duty-cycle becomes closer to 50% when the division ratio is an increasing odd number. For each division ratio, the output duty-cycle remains constant, with different input frequencies from GHz down to kHz ranges, with different temperatures and power supply voltages. This thesis provides an explanation of the design details and test results. A Phase Locked-Loop (PLL) based frequency synthesizer can generate different output frequencies. A programmable frequency divider is an important component of this type of PLL. Since bandwidth is expensive, it is preferred to reduce the frequency channel distance of a frequency synthesizer. Using a fractional programmable divider, the frequency channel distance of a PLL can be reduced, without reducing the reference frequency or increasing the settling time of the PLL. A frequency synthesizer with a programmable fractional divider is designed and fabricated. A brief description of the PLL design and test results are presented in this dissertation

A design methodology to enable sampling PLLs to synthesise fractional-N frequencies

A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N phase-locked loop (FN-PLL) and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed fractional-N sampling phase-locked loop (FN-SPLL)