7,139 research outputs found
Applying Formal Methods to Networking: Theory, Techniques and Applications
Despite its great importance, modern network infrastructure is remarkable for
the lack of rigor in its engineering. The Internet which began as a research
experiment was never designed to handle the users and applications it hosts
today. The lack of formalization of the Internet architecture meant limited
abstractions and modularity, especially for the control and management planes,
thus requiring for every new need a new protocol built from scratch. This led
to an unwieldy ossified Internet architecture resistant to any attempts at
formal verification, and an Internet culture where expediency and pragmatism
are favored over formal correctness. Fortunately, recent work in the space of
clean slate Internet design---especially, the software defined networking (SDN)
paradigm---offers the Internet community another chance to develop the right
kind of architecture and abstractions. This has also led to a great resurgence
in interest of applying formal methods to specification, verification, and
synthesis of networking protocols and applications. In this paper, we present a
self-contained tutorial of the formidable amount of work that has been done in
formal methods, and present a survey of its applications to networking.Comment: 30 pages, submitted to IEEE Communications Surveys and Tutorial
Online Scheduled Execution of Quantum Circuits Protected by Surface Codes
Quantum circuits are the preferred formalism for expressing quantum
information processing tasks. Quantum circuit design automation methods mostly
use a waterfall approach and consider that high level circuit descriptions are
hardware agnostic. This assumption has lead to a static circuit perspective:
the number of quantum bits and quantum gates is determined before circuit
execution and everything is considered reliable with zero probability of
failure. Many different schemes for achieving reliable fault-tolerant quantum
computation exist, with different schemes suitable for different architectures.
A number of large experimental groups are developing architectures well suited
to being protected by surface quantum error correcting codes. Such circuits
could include unreliable logical elements, such as state distillation, whose
failure can be determined only after their actual execution. Therefore,
practical logical circuits, as envisaged by many groups, are likely to have a
dynamic structure. This requires an online scheduling of their execution: one
knows for sure what needs to be executed only after previous elements have
finished executing. This work shows that scheduling shares similarities with
place and route methods. The work also introduces the first online schedulers
of quantum circuits protected by surface codes. The work also highlights
scheduling efficiency by comparing the new methods with state of the art static
scheduling of surface code protected fault-tolerant circuits.Comment: accepted in QI
Cross-level Validation of Topological Quantum Circuits
Quantum computing promises a new approach to solving difficult computational
problems, and the quest of building a quantum computer has started. While the
first attempts on construction were succesful, scalability has never been
achieved, due to the inherent fragile nature of the quantum bits (qubits). From
the multitude of approaches to achieve scalability topological quantum
computing (TQC) is the most promising one, by being based on an flexible
approach to error-correction and making use of the straightforward
measurement-based computing technique. TQC circuits are defined within a large,
uniform, 3-dimensional lattice of physical qubits produced by the hardware and
the physical volume of this lattice directly relates to the resources required
for computation. Circuit optimization may result in non-intuitive mismatches
between circuit specification and implementation. In this paper we introduce
the first method for cross-level validation of TQC circuits. The specification
of the circuit is expressed based on the stabilizer formalism, and the
stabilizer table is checked by mapping the topology on the physical qubit
level, followed by quantum circuit simulation. Simulation results show that
cross-level validation of error-corrected circuits is feasible.Comment: 12 Pages, 5 Figures. Comments Welcome. RC2014, Springer Lecture Notes
on Computer Science (LNCS) 8507, pp. 189-200. Springer International
Publishing, Switzerland (2014), Y. Shigeru and M.Shin-ichi (Eds.
Model-based dependability analysis : state-of-the-art, challenges and future outlook
Abstract: Over the past two decades, the study of model-based dependability analysis has gathered significant research interest. Different approaches have been developed to automate and address various limitations of classical dependability techniques to contend with the increasing complexity and challenges of modern safety-critical system. Two leading paradigms have emerged, one which constructs predictive system failure models from component failure models compositionally using the topology of the system. The other utilizes design models - typically state automata - to explore system behaviour through fault injection. This paper reviews a number of prominent techniques under these two paradigms, and provides an insight into their working mechanism, applicability, strengths and challenges, as well as recent developments within these fields. We also discuss the emerging trends on integrated approaches and advanced analysis capabilities. Lastly, we outline the future outlook for model-based dependability analysis
Synthesis of Topological Quantum Circuits
Topological quantum computing has recently proven itself to be a very
powerful model when considering large- scale, fully error corrected quantum
architectures. In addition to its robust nature under hardware errors, it is a
software driven method of error corrected computation, with the hardware
responsible for only creating a generic quantum resource (the topological
lattice). Computation in this scheme is achieved by the geometric manipulation
of holes (defects) within the lattice. Interactions between logical qubits
(quantum gate operations) are implemented by using particular arrangements of
the defects, such as braids and junctions. We demonstrate that junction-based
topological quantum gates allow highly regular and structured implementation of
large CNOT (controlled-not) gate networks, which ultimately form the basis of
the error corrected primitives that must be used for an error corrected
algorithm. We present a number of heuristics to optimise the area of the
resulting structures and therefore the number of the required hardware
resources.Comment: 7 Pages, 10 Figures, 1 Tabl
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