A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

Design and FPGA Implementation of Channelizer & Frequency Hopping for Advanced SATCOM System

Advanced satellite communication systems should be capable of preventing unauthorized access or exploitation of communication services by adversaries. This can be achieved by use of wideband multi -channel digital transceivers which employ channelizer to extract the channel of interest from digitized RF bands for further baseband processing. Various anti-jamming techniques like Frequency hopping are used to prevent the systems from intentional jamming by the hostile systems. This paper presents an efficient channelizer architecture which supports wideband as well as narrowband channels with programmable channel bandwidth followed by frequency hopping for the proposed SATCOM system. The target design is a flexible channelization unit which divides the incoming data links of 11 MHz bandwidth into two data links in granularity of 0.5 MHz depending upon user requirements. First link is further sub-channelized into two sub-links each having a bandwidth of 25 KHz that is frequency hopped at a user programmable rate with desired random sequence. The same channelizer can be well applicablein any software defined radio receiver platforms due to flexibility of the design. Proposed design is tested on target hardware XilinxVirtex-IV FPGA xc4vsx35-10ff668. The design and implementation of the channelizer and frequency hopping technique arediscussed in detail

Development and testing of the RHINO host streamed data acquisition framework

This project focuses on developing a supporting framework for integrating the Reconfigurable Hardware INterface for computing and radiO (RHINO) with a Personal Computer (PC) host in order to facilitate the development of Software Defined Radio (SDR) applications built using a hybrid RHINO/multicore PC system. The supporting framework that is the focus of this dissertation is designed around two main parts: a) resources for integrating the GNU Radio framework with the RHINO platform to allow data streams to be sent from RHINO to be processed by GNU Radio, and b) a concise and highly efficient C code module with accompanying Application Program Interface (API) that will receive streamed data from RHINO and provide data marshalling facilities to gather and dispatch blocks of data for further processing using C/C++ routines. The methodology followed in this research project involves investigating real-time streaming techniques using User Datagram Protocol (UDP) packets, furthermore, investigating how GNU Radio high-level SDR development framework can be integrated into the real-time data acquisition systems such as in the case of this project with RHINO. The literature for real-time processing requirements for the streamer framework was reviewed. The guidelines to implement a high performance, low latency and maximum throughput for streaming will consequently be presented and the proposed design motivated. The results achieved demonstrate an efficient data streaming system. The objectives of implementing RHINO data acquisition system through integration with standard C/C++ code and GNU Radio were satisfactorily met. The system was tested with real-time Radio Frequency (RF) demodulation. The system captures a pair of an In-phase/Quadrature signal (I/Q) sample at a time, which is one packet. The results show that data can be streamed from the RHINO board to GNU Radio over GbE with a minimum capturing latency of 10.2μs for 2 0 packet size and an average data capturing throughput of 0.54 Mega Bytes per second (MBps). The capturing latency, in this case, is the time taken from the time of the request to receiving the data. The FM receiver case study successfully demonstrated results of a demodulated FM signal of a 94.5 Mega Hetz (MHz) radio station. Further recommendations include making use of the 10GbE port on RHINO for data streaming purposes. 10GbE port on RHINO can be used together with GNU Radio to improve the speed of the RHINO streamer

Design and Implementation of an RF Front-End for Software Defined Radios

Software Defined Radios have brought a major reformation in the design standards for radios, in which a large portion of the functionality is implemented through pro­ grammable signal processing devices, giving the radio the ability to change its op­ erating parameters to accommodate new features and capabilities. A software radio approach reduces the content of radio frequency and other analog components of the traditional radios and emphasizes digital signal processing to enhance overall receiver flexibility. Field Programmable Gate Arrays (FPGA) are a suitable technology for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability. Software defined radio is a very broad field, encompassing the design of various technologies all the way from the antenna to RF, IF, and baseband digital design. The RF section primarily consists of analog hardware modules. The IF and baseband sections are primarily digital. It is the general process of the radio to convert the incoming signal from RF to IF and then IF to baseband for better signal processing system. In this thesis, some of major building blocks of a Software defined radio are de­ signed and implemented using FPGAs. The design of a Digital front end, which provides the bridge between the baseband and analog RF portions of a wireless receiver, is synthesized. The Digital front end receiver consists of a digital down converter(DDC) which in turn comprises of a direct digital frequency synthesizer (DDFS), a phase accumulator and a low pass filter. The signal processing block of the DDFS is executed using Co-ordinate Rotation Digital Computer (CORDIC) iii Abstract algorithm. Cascaded-Integrator-Comb filters (CIC) are implemented for changing the sample rate of the incoming data. Application of a DDC includes software ra­ dios, multicarrier, multimode digital receivers, micro and pico cell systems,broadband data applications, instrumentation and test equipment and in-building wireless tele­ phony. Also, in this thesis, interfaces for connecting Texas Instruments high speed and high resolution Analog-to-Digital converters (ADC) and Digital-to-Analog converters (DAC) with Xilinx Virtex-5 FPGAs are also implemented and demonstrated

Radio over fiber enabling PON fronthaul in a two-tiered cloud

Avec l’avènement des objets connectés, la bande passante nécessaire dépasse la capacité des interconnections électriques et interface sans fils dans les réseaux d’accès mais aussi dans les réseaux coeurs. Des systèmes photoniques haute capacité situés dans les réseaux d’accès utilisant la technologie radio sur fibre systèmes ont été proposés comme solution dans les réseaux sans fil de 5e générations. Afin de maximiser l’utilisation des ressources des serveurs et des ressources réseau, le cloud computing et des services de stockage sont en cours de déploiement. De cette manière, les ressources centralisées pourraient être diffusées de façon dynamique comme l’utilisateur final le souhaite. Chaque échange nécessitant une synchronisation entre le serveur et son infrastructure, une couche physique optique permet au cloud de supporter la virtualisation des réseaux et de les définir de façon logicielle. Les amplificateurs à semi-conducteurs réflectifs (RSOA) sont une technologie clé au niveau des ONU(unité de communications optiques) dans les réseaux d’accès passif (PON) à fibres. Nous examinons ici la possibilité d’utiliser un RSOA et la technologie radio sur fibre pour transporter des signaux sans fil ainsi qu’un signal numérique sur un PON. La radio sur fibres peut être facilement réalisée grâce à l’insensibilité a la longueur d’onde du RSOA. Le choix de la longueur d’onde pour la couche physique est cependant choisi dans les couches 2/3 du modèle OSI. Les interactions entre la couche physique et la commutation de réseaux peuvent être faites par l’ajout d’un contrôleur SDN pour inclure des gestionnaires de couches optiques. La virtualisation réseau pourrait ainsi bénéficier d’une couche optique flexible grâce des ressources réseau dynamique et adaptée. Dans ce mémoire, nous étudions un système disposant d’une couche physique optique basé sur un RSOA. Celle-ci nous permet de façon simultanée un envoi de signaux sans fil et le transport de signaux numérique au format modulation tout ou rien (OOK) dans un système WDM(multiplexage en longueur d’onde)-PON. Le RSOA a été caractérisé pour montrer sa capacité à gérer une plage dynamique élevée du signal sans fil analogique. Ensuite, les signaux RF et IF du système de fibres sont comparés avec ses avantages et ses inconvénients. Finalement, nous réalisons de façon expérimentale une liaison point à point WDM utilisant la transmission en duplex intégral d’un signal wifi analogique ainsi qu’un signal descendant au format OOK. En introduisant deux mélangeurs RF dans la liaison montante, nous avons résolu le problème d’incompatibilité avec le système sans fil basé sur le TDD (multiplexage en temps duplexé).With the advent of IoT (internet of things) bandwidth requirements triggered by aggregated wireless connections have exceeded the fundamental limitation of copper and microwave based wireless backhaul and fronthaul networks. High capacity photonic fronthaul systems employing radio over fiber technology has been proposed as the ultimate solution for 5G wireless system. To maximize utilization of server and network resources, cloud computing and storage based services are being deployed. In this manner, centralized resources could be dynamically streamed to the end user as requested. Since on demand resource provision requires the orchestration between the server and network infrastructure, a smart photonic (physical layer)PHY enabled cloud is foreseen to support network virtualization and software defined network. RSOAs (Reflective Semiconductor Optical Amplifier) are being investigated as key enablers of the colorless ONU(Optical Network Unit) solution in PON (Passive Optical Network). We examine the use of an RSOA in radio over fiber systems to transport wireless signals over a PON simultaneously with digital data. Radio over fiber systems with flexible wavelength allocation could be achieved thanks to the colorless operation of the RSOA and wavelength reuse technique. The wavelength flexibility in optical PHY are inline with the paradigm of software defined network (SDN) in OSI layer 2/3. The orchestration between optical PHY and network switching fabric could be realized by extending the SDN controller to include optical layer handlers. Network virtualization could also benefit from the flexible optical PHY through dynamic and tailored optical network resource provision. In this thesis, we investigate an optical PHY system based on RSOA enabling both analog wireless signal and digital On-Off Keying (OOK) transportation within WDM (Wavelength Division Multiplexing) PON architecture. The RSOA has been characterized to show its potential ability to handle high dynamic range analog wireless signal. Then the RF and IF radio over fiber scheme is compared with its pros and cons. Finally we perform the experiment to shown a point to point WDM link with full duplex transmission of analog WiFi signal with downlink OOK signal. By introducing two RF mixer in the uplink, we have solved the incompatible problem with TDD (Time Division Duplex) based wireless system

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

IF-Sampling Digital Beamforming with Bit-Stream Processing.

Beamforming in receivers improves signal-to-noise ratio (SNR), and enables spatial filtering of incoming signals, which helps reject interferers. However, power consump-tion, area, and routing complexity needed with an increasing number of elements have been a bottleneck to implementing efficient beamforming systems. Especially, digital beamforming (DBF), despite its versatility, has not been attractive for low-cost on-chip implementation due to its high power consumption and large die area for multiple high-performance analog-to-digital converters (ADCs) and an intensive digital signal process-ing (DSP) unit. This thesis presents a new DBF receiver architecture with direct intermediate frequency (IF) sampling. By adopting IF sampling in DBF, a digital-intensive beamforming receiver, which provides highly flexible and accurate beamforming, is achieved. The IF-sampling DBF receiver architecture is efficiently implemented with continuous-time band-pass delta-sigma modulators (CTBPDSMs) and bit-stream processing (BSP). They have been separately investigated, and have not been considered for DBF until now. The unique combination of CTBPDSMs and BSP enables low-power and area-efficient DBF by removing the need for digital multipliers and multiple decimators. Two prototype digital beamformers (prototype I and prototype II) are fabricated in 65 nm complementary metal-oxide-semiconductor (CMOS) technology. The prototype I forms a single beam from four 265 MHz IF inputs, and an array signal-to-noise-plus-distortion ratio (SNDR) of 56.6 dB is achieved over a 10 MHz bandwidth. The prototype I consumes 67.2 mW, and occupies 0.16 mm2. The prototype II forms two simultaneous beams from eight 260 MHz IF inputs, and an array SNDR of 63.3 dB is achieved over a 10 MHz bandwidth. The prototype II consumes 123.7 mW, and occupies 0.28 mm2. The two prototypes are the first on-chip implementation of IF-sampling DBF.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/116778/1/jaehun_1.pd

Calibrated Continuous-Time Sigma-Delta Modulators

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry